These patches were previously posted in March as RFC's. These patches just
reformat the floating point move insns to make it easier to figure out which
constraints and attributes are used for particular alternatives.
I have built the compiler on a little endian power8 system with all 5 patches
applied and it bootstraps without error. There were no regressions in make
check output. Can I check these patches in?
This is patch #3 of 5.
2018-05-03 Michael Meissner <meiss...@linux.vnet.ibm.com>
* config/rs6000/rs6000.md (mov<mode>_hardfloat64, FMOVE64):
Reformat alternatives and attributes so it is easier to identify
which constraints/attributes go with which instruction.
--
Michael Meissner, IBM
IBM, M/S 2506R, 550 King Street, Littleton, MA 01460-6245, USA
email: meiss...@linux.ibm.com, phone: +1 (978) 899-4797
Index: gcc/config/rs6000/rs6000.md
===================================================================
--- gcc/config/rs6000/rs6000.md (revision 259883)
+++ gcc/config/rs6000/rs6000.md (working copy)
@@ -7453,9 +7453,25 @@ (define_insn "*mov<mode>_softfloat32"
; ld/std require word-aligned displacements -> 'Y' constraint.
; List Y->r and r->Y before r->r for reload.
+
+;; STFD LFD FMR LXSD STXSD
+;; LXSDX STXSDX XXLOR XXLXOR LI 0
+;; STD LD MR MT<SPR> MF<SPR>
+;; NOP MFTGPR MFFGPR MTVSRD MFVSRD
+
(define_insn "*mov<mode>_hardfloat64"
- [(set (match_operand:FMOVE64 0 "nonimmediate_operand"
"=m,d,d,<f64_p9>,wY,<f64_av>,Z,<f64_vsx>,<f64_vsx>,!r,Y,r,!r,*c*l,!r,*h,r,wg,r,<f64_dm>")
- (match_operand:FMOVE64 1 "input_operand"
"d,m,d,wY,<f64_p9>,Z,<f64_av>,<f64_vsx>,<zero_fp>,<zero_fp>,r,Y,r,r,h,0,wg,r,<f64_dm>,r"))]
+ [(set (match_operand:FMOVE64 0 "nonimmediate_operand"
+ "=m, d, d, <f64_p9>, wY,
+ <f64_av>, Z, <f64_vsx>, <f64_vsx>, !r,
+ Y, r, !r, *c*l, !r,
+ *h, r, wg, r, <f64_dm>")
+
+ (match_operand:FMOVE64 1 "input_operand"
+ "d, m, d, wY, <f64_p9>,
+ Z, <f64_av>, <f64_vsx>, <zero_fp>, <zero_fp>,
+ r, Y, r, r, h,
+ 0, wg, r, <f64_dm>, r"))]
+
"TARGET_POWERPC64 && TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT
&& (gpc_reg_operand (operands[0], <MODE>mode)
|| gpc_reg_operand (operands[1], <MODE>mode))"
@@ -7480,7 +7496,12 @@ (define_insn "*mov<mode>_hardfloat64"
mffgpr %0,%1
mfvsrd %0,%x1
mtvsrd %x0,%1"
- [(set_attr "type"
"fpstore,fpload,fpsimple,fpload,fpstore,fpload,fpstore,veclogical,veclogical,integer,store,load,*,mtjmpr,mfjmpr,*,mftgpr,mffgpr,mftgpr,mffgpr")
+ [(set_attr "type"
+ "fpstore, fpload, fpsimple, fpload, fpstore,
+ fpload, fpstore, veclogical, veclogical, integer,
+ store, load, *, mtjmpr, mfjmpr,
+ *, mftgpr, mffgpr, mftgpr, mffgpr")
+
(set_attr "size" "64")
(set_attr "length" "4")])
