On Mon, 26 Mar 2018, Peter Bergner wrote:
> PR84878 shows an example where we segv while creating data dependence edges
> for SMS.
>
> ddg.c:add_cross_iteration_register_deps():
>
> /* Create inter-loop true dependences and anti dependences. */
> for (r_use = DF_REF_CHAIN (last_def); r_use != NULL; r_use = r_use->next)
> {
> rtx_insn *use_insn = DF_REF_INSN (r_use->ref);
> ^^^^ segv's
>
> We currently have:
> (gdb) pr def_insn
> (insn 331 321 332 12 (parallel [
> (set (reg:V4SI 239 [ vect__4.11 ])
> (unspec:V4SI [
> (reg:V4SF 134 [ vect_cst__39 ])
> (const_int 0 [0])
> ] UNSPEC_VCTSXS))
> (set (reg:SI 110 vscr)
> (unspec:SI [
> (const_int 0 [0])
> ] UNSPEC_SET_VSCR))
> ]) "bug.i":9 1812 {altivec_vctsxs}
> (expr_list:REG_UNUSED (reg:V4SI 239 [ vect__4.11 ])
> (nil)))
> (gdb) p DF_REF_REGNO (last_def)
> $4 = 110
>
> So we're looking at the definition of the VSCR hard register, which is a
> global register (ie, global_regs[110] == 1), but there are no following
> explicit uses of the VSCR reg, so:
>
> (gdb) p DF_REF_INSN_INFO(r_use->ref)
> $5 = (df_insn_info *) 0x0
>
> DF_REF_INSN(r_use->ref) deferences DF_REF_INSN_INFO(r_use->ref), so we segv.
>
> The following patch fixes the problems by simply skiping over the "uses"
> that do not have insn info (ie, no explicit uses or artificial ones).
>
> This passed bootstrap and regtesting with no regressions on powerpc64-linux.
> Ok for trunk?
>
> Peter
>
>
> gcc/
> PR rtl-optimization/84878
> * ddg.c (add_cross_iteration_register_deps): Skip over uses that do
> not correspond to explicit register references.
>
> gcc/testsuite/
> PR rtl-optimization/84878
> * gcc.dg/pr84878.c: New test.
>
> Index: gcc/ddg.c
> ===================================================================
> --- gcc/ddg.c (revision 258802)
> +++ gcc/ddg.c (working copy)
> @@ -295,6 +295,11 @@ add_cross_iteration_register_deps (ddg_p
> /* Create inter-loop true dependences and anti dependences. */
> for (r_use = DF_REF_CHAIN (last_def); r_use != NULL; r_use = r_use->next)
> {
> + /* PR84878: Some definitions of global hard registers may not have
> + any following uses or they may be artificial, so skip them. */
> + if (DF_REF_INSN_INFO (r_use->ref) == NULL)
> + continue;
> +
To me a better check would be DF_REF_IS_ARTIFICIAL (r_use->ref). But
I'm not sure simply ignoring those will be correct? In fact
artifical refs do have a basic-block, so
> rtx_insn *use_insn = DF_REF_INSN (r_use->ref);
>
> if (BLOCK_FOR_INSN (use_insn) != g->bb)
should use DF_REF_BB (r_use->ref) instead of indirection through
DF_REF_INSN. Still use_insn is used later but then if the
artificial ref is in side g->bb we should better give up here?
We don't seem to have use_nodes for these "non-insns".
Somebody with more insight on DF should chime in here and tell
me what those "artificial" refs are about ... there's
/* If this flag is set for an artificial use or def, that ref
logically happens at the top of the block. If it is not set
for an artificial use or def, that ref logically happens at the
bottom of the block. This is never set for regular refs. */
DF_REF_AT_TOP = 1 << 1,
so this is kind-of global regs being live across all BBs? This sounds
a bit stupid to me, but well ... IMHO those refs should be at
specific insns like calls.
So maybe, with a big fat comment, it is OK to ignore artificial
refs in this loop...
Richard.
> Index: gcc/testsuite/gcc.dg/pr84878.c
> ===================================================================
> --- gcc/testsuite/gcc.dg/pr84878.c (revision 0)
> +++ gcc/testsuite/gcc.dg/pr84878.c (working copy)
> @@ -0,0 +1,20 @@
> +/* PR rtl-optimization/84878 */
> +/* { dg-do compile { target { powerpc*-*-* } } } */
> +/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } {
> "-mcpu=G5" } } */
> +/* { dg-require-effective-target powerpc_altivec_ok } */
> +/* { dg-options "-O2 -mcpu=G5 -fmodulo-sched -ftree-vectorize -funroll-loops
> -fassociative-math -fno-signed-zeros -fno-trapping-math" } */
> +
> +int ek;
> +float zu;
> +
> +int
> +k5 (int ks)
> +{
> + while (ek < 1)
> + {
> + ks += (int)(0x1000000 + zu + !ek);
> + ++ek;
> + }
> +
> + return ks;
> +}
>
>
--
Richard Biener <rguent...@suse.de>
SUSE LINUX GmbH, GF: Felix Imendoerffer, Jane Smithard, Graham Norton, HRB
21284 (AG Nuernberg)
