This patch renames the mode_supports_vsx_dform_quad function and changes all of
the callers. I'm thinking about enhancing the addressing parts in the
secondary reload support, and I wanted a more logical naming scheme. There
will be mode_supports_d_form for offsettable addresses of any form, and
mode_supports_ds_form for addresses where the bottom 2 bits are 0 in the
future.
I have built bootstrap compilers with the first 4 patches including this patch
on both big and little endian power8 systems. There were no regressions.
2018-03-21 Michael Meissner <meiss...@linux.vnet.ibm.com>
* config/rs6000/rs6000.c (mode_supports_dq_form): Rename
mode_supports_vsx_dform_quad to mode_supports_dq_form.
(mode_supports_vsx_dform_quad): Likeise.
(quad_address_p): Likewise.
(reg_offset_addressing_ok_p): Likewise.
(offsettable_ok_by_alignment): Likewise.
(rs6000_legitimate_offset_address_p): Likewise.
(legitimate_lo_sum_address_p): Likewise.
(rs6000_legitimize_address): Likewise.
(rs6000_legitimize_reload_address): Likewise.
(rs6000_secondary_reload_inner): Likewise.
(rs6000_preferred_reload_class): Likewise.
(rs6000_output_move_128bit): Likewise.
--
Michael Meissner, IBM
IBM, M/S 2506R, 550 King Street, Littleton, MA 01460-6245, USA
email: meiss...@linux.vnet.ibm.com, phone: +1 (978) 899-4797
Index: gcc/config/rs6000/rs6000.c
===================================================================
--- gcc/config/rs6000/rs6000.c (revision 258719)
+++ gcc/config/rs6000/rs6000.c (working copy)
@@ -649,7 +649,7 @@ mode_supports_vmx_dform (machine_mode mo
is more limited than normal d-form addressing in that the offset must be
aligned on a 16-byte boundary. */
static inline bool
-mode_supports_vsx_dform_quad (machine_mode mode)
+mode_supports_dq_form (machine_mode mode)
{
return ((reg_addr[mode].addr_mask[RELOAD_REG_ANY] & RELOAD_REG_QUAD_OFFSET)
!= 0);
@@ -8107,7 +8107,7 @@ quad_address_p (rtx addr, machine_mode m
if (legitimate_indirect_address_p (addr, strict))
return true;
- if (VECTOR_MODE_P (mode) && !mode_supports_vsx_dform_quad (mode))
+ if (VECTOR_MODE_P (mode) && !mode_supports_dq_form (mode))
return false;
if (GET_CODE (addr) != PLUS)
@@ -8289,7 +8289,7 @@ reg_offset_addressing_ok_p (machine_mode
IEEE 128-bit floating point that is passed in a single vector
register. */
if (VECTOR_MEM_ALTIVEC_OR_VSX_P (mode))
- return mode_supports_vsx_dform_quad (mode);
+ return mode_supports_dq_form (mode);
break;
case E_V2SImode:
@@ -8356,7 +8356,7 @@ offsettable_ok_by_alignment (rtx op, HOS
/* ISA 3.0 vector d-form addressing is restricted, don't allow
SYMBOL_REF. */
- if (mode_supports_vsx_dform_quad (mode))
+ if (mode_supports_dq_form (mode))
return false;
dsize = GET_MODE_SIZE (mode);
@@ -8527,7 +8527,7 @@ rs6000_legitimate_offset_address_p (mach
return false;
if (!INT_REG_OK_FOR_BASE_P (XEXP (x, 0), strict))
return false;
- if (mode_supports_vsx_dform_quad (mode))
+ if (mode_supports_dq_form (mode))
return quad_address_p (x, mode, strict);
if (!reg_offset_addressing_ok_p (mode))
return virtual_stack_registers_memory_p (x);
@@ -8645,7 +8645,7 @@ legitimate_lo_sum_address_p (machine_mod
if (!INT_REG_OK_FOR_BASE_P (XEXP (x, 0), strict))
return false;
/* quad word addresses are restricted, and we can't use LO_SUM. */
- if (mode_supports_vsx_dform_quad (mode))
+ if (mode_supports_dq_form (mode))
return false;
x = XEXP (x, 1);
@@ -8710,7 +8710,7 @@ rs6000_legitimize_address (rtx x, rtx ol
unsigned int extra;
if (!reg_offset_addressing_ok_p (mode)
- || mode_supports_vsx_dform_quad (mode))
+ || mode_supports_dq_form (mode))
{
if (virtual_stack_registers_memory_p (x))
return x;
@@ -9454,7 +9454,7 @@ rs6000_legitimize_reload_address (rtx x,
int ind_levels ATTRIBUTE_UNUSED, int *win)
{
bool reg_offset_p = reg_offset_addressing_ok_p (mode);
- bool quad_offset_p = mode_supports_vsx_dform_quad (mode);
+ bool quad_offset_p = mode_supports_dq_form (mode);
/* Nasty hack for vsx_splat_v2df/v2di load from mem, which takes a
DFmode/DImode MEM. Ditto for ISA 3.0 vsx_splat_v4sf/v4si. */
@@ -9742,7 +9742,7 @@ static bool
rs6000_legitimate_address_p (machine_mode mode, rtx x, bool reg_ok_strict)
{
bool reg_offset_p = reg_offset_addressing_ok_p (mode);
- bool quad_offset_p = mode_supports_vsx_dform_quad (mode);
+ bool quad_offset_p = mode_supports_dq_form (mode);
/* If this is an unaligned stvx/ldvx type address, discard the outer AND. */
if (VECTOR_MEM_ALTIVEC_P (mode)
@@ -20409,7 +20409,7 @@ rs6000_secondary_reload_inner (rtx reg,
}
}
- else if (mode_supports_vsx_dform_quad (mode) && CONST_INT_P (op1))
+ else if (mode_supports_dq_form (mode) && CONST_INT_P (op1))
{
if (((addr_mask & RELOAD_REG_QUAD_OFFSET) == 0)
|| !quad_address_p (addr, mode, false))
@@ -20450,7 +20450,7 @@ rs6000_secondary_reload_inner (rtx reg,
}
/* Quad offsets are restricted and can't handle normal addresses. */
- else if (mode_supports_vsx_dform_quad (mode))
+ else if (mode_supports_dq_form (mode))
{
emit_insn (gen_rtx_SET (scratch, addr));
new_addr = scratch;
@@ -20645,7 +20645,7 @@ rs6000_preferred_reload_class (rtx x, en
/* D-form addressing can easily reload the value. */
if (mode_supports_vmx_dform (mode)
- || mode_supports_vsx_dform_quad (mode))
+ || mode_supports_dq_form (mode))
return rclass;
/* If this is a scalar floating point value and we don't have D-form
@@ -21048,7 +21048,7 @@ rs6000_output_move_128bit (rtx operands[
else if (TARGET_VSX && dest_vsx_p)
{
- if (mode_supports_vsx_dform_quad (mode)
+ if (mode_supports_dq_form (mode)
&& quad_address_p (XEXP (src, 0), mode, true))
return "lxv %x0,%1";
@@ -21086,7 +21086,7 @@ rs6000_output_move_128bit (rtx operands[
else if (TARGET_VSX && src_vsx_p)
{
- if (mode_supports_vsx_dform_quad (mode)
+ if (mode_supports_dq_form (mode)
&& quad_address_p (XEXP (dest, 0), mode, true))
return "stxv %x1,%0";
