Hi Carl,
On Mon, Mar 12, 2018 at 08:21:08AM -0700, Carl Love wrote:
> The following patch add support for the vec_permxor builtins.
>
> Note the change in file rs6000-p8swap.c is actually a fix for the
> existing define_insn "crypto_vpermxor in crypto.md. The fix disables
> swap optimization for the vpermxor instruction. Without this fix
> optimization with -O1 and above results in the upper and lower 64-bits
> of the three operands are swapped messing up the indexing specified by
> the third operand. This change will need to be back ported to GCC 6
> and 7.
> 2018-03-12 Carl Love <c...@us.ibm.com>
>
> * config/rs6000/rs6000-c.c: Add macro definitions for
> ALTIVEC_BUILTIN_VEC_PERM.
ALTIVEC_BUILTIN_VEC_PERMXOR.
> * config/rs6000/rs6000.h: Add #define for vec_permxor builtin.
> * config/rs6000/rs6000-builtin.def: Add macro expansions for VPERMXOR.
> * config/rs6000/altivec.md: Add define_insn for altivec-vpermxor.
altivec_vpermxor.
Please write this like:
(altivec_vpermxor): New define_expand.
> Add UNSPEC_VNOR, define_insn altivec_vnor_v16qi3.
There already is nor<mode>3 for BOOL_128 (so norv16qi3 for this).
But you probably want to use one_cmpl<mode>2 instead (which ends up as
*one_cmpl<mode>3_internal for BOOL_128, *one_cmplv16qi3_internal here
(the "3" is a misnomer), the expander is one_cmplv16qi2).
> --- /dev/null
> +++ b/gcc/testsuite/gcc.target/powerpc/builtins-7-runnable.c
> @@ -0,0 +1,112 @@
> +/* { dg-do run { target { powerpc*-*-* && { lp64 && p8vector_hw } } } } */
> +/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } {
> "-mcpu=power8" } } */
> +/* { dg-options "-mcpu=power8 -O2" } */
Does this need lp64?
Rest looks good.
Segher
