Hello!
It turned out that *andndi3_doubleword pattern needs earlyclobber on
the output operand of its (=r,r,rm) alternative to prevent partial
regs of the first split instruction from clobbering input operands of
the second insn.The patch also adds a couple of alternatives with
matching input and output operands that are guaranteed to not clobber
the other input operand in a sequence of split insns of a
three-operand non-destructive insn.
2018-01-26 Uros Bizjak <ubiz...@gmail.com>
PR target/81763
* config/i386/i386.md (*andndi3_doubleword): Add earlyclobber
to (=&r,r,rm) alternative. Add (=r,0,rm) and (=r,r,0) alternatives.
Bootstrapped and regression tested on x86_64-linux-gnu {,-m32}.
Committed to mainline, will be bacported to gcc-7 branch early next week.
Uros.
diff --git a/gcc/config/i386/i386.md b/gcc/config/i386/i386.md
index 5cd3ec0..fe9649d 100644
--- a/gcc/config/i386/i386.md
+++ b/gcc/config/i386/i386.md
@@ -9250,14 +9250,14 @@
})
(define_insn "*andndi3_doubleword"
- [(set (match_operand:DI 0 "register_operand" "=r,&r")
+ [(set (match_operand:DI 0 "register_operand" "=&r,r,r,&r")
(and:DI
- (not:DI (match_operand:DI 1 "register_operand" "r,0"))
- (match_operand:DI 2 "nonimmediate_operand" "rm,rm")))
+ (not:DI (match_operand:DI 1 "register_operand" "r,0,r,0"))
+ (match_operand:DI 2 "nonimmediate_operand" "rm,rm,0,rm")))
(clobber (reg:CC FLAGS_REG))]
"!TARGET_64BIT && TARGET_STV && TARGET_SSE2"
"#"
- [(set_attr "isa" "bmi,*")])
+ [(set_attr "isa" "bmi,bmi,bmi,*")])
(define_split
[(set (match_operand:DI 0 "register_operand")
