v2: Rebased after the big SVE commits
Remove the remaining uses of '*' from aarch64.md.
Using '*' in alternatives is typically incorrect as it tells the register
allocator to ignore those alternatives. Also add a missing '?' so we
prefer a floating point register for same-size int<->fp conversions.
Passes regress & bootstrap, OK for commit?
ChangeLog:
2018-01-16 Wilco Dijkstra <wdijk...@arm.com>
* config/aarch64/aarch64.md (mov<mode>): Remove '*' in alternatives.
(movsi_aarch64): Likewise.
(load_pairsi): Likewise.
(load_pairdi): Likewise.
(store_pairsi): Likewise.
(store_pairdi): Likewise.
(load_pairsf): Likewise.
(load_pairdf): Likewise.
(store_pairsf): Likewise.
(store_pairdf): Likewise.
(zero_extend): Likewise.
(fcvt_target): Add '?' to prefer w over r.
gcc/testsuite/
* gcc.target/aarch64/vfp-1.c: Update test.
--
diff --git a/gcc/config/aarch64/aarch64.md b/gcc/config/aarch64/aarch64.md
index
e52e8350a203b288208c1acb12c8b881d5e8039a..088ed8cb0aad0be08a7e19064708ea14499230f2
100644
--- a/gcc/config/aarch64/aarch64.md
+++ b/gcc/config/aarch64/aarch64.md
@@ -907,8 +907,8 @@ (define_expand "mov<mode>"
)
(define_insn "*mov<mode>_aarch64"
- [(set (match_operand:SHORT 0 "nonimmediate_operand" "=r,r, *w,r ,r,*w, m,
m, r,*w,*w")
- (match_operand:SHORT 1 "aarch64_mov_operand" " r,M,D<hq>,Usv,m,
m,rZ,*w,*w, r,*w"))]
+ [(set (match_operand:SHORT 0 "nonimmediate_operand" "=r,r, w,r ,r,w,
m,m,r,w,w")
+ (match_operand:SHORT 1 "aarch64_mov_operand" "
r,M,D<hq>,Usv,m,m,rZ,w,w,r,w"))]
"(register_operand (operands[0], <MODE>mode)
|| aarch64_reg_or_zero (operands[1], <MODE>mode))"
{
@@ -974,7 +974,7 @@ (define_expand "mov<mode>"
(define_insn_and_split "*movsi_aarch64"
[(set (match_operand:SI 0 "nonimmediate_operand" "=r,k,r,r,r,r, r,w, m, m,
r, r, w,r,w, w")
- (match_operand:SI 1 "aarch64_mov_operand" "
r,r,k,M,n,Usv,m,m,rZ,*w,Usa,Ush,rZ,w,w,Ds"))]
+ (match_operand:SI 1 "aarch64_mov_operand" "
r,r,k,M,n,Usv,m,m,rZ,w,Usa,Ush,rZ,w,w,Ds"))]
"(register_operand (operands[0], SImode)
|| aarch64_reg_or_zero (operands[1], SImode))"
"@
@@ -1281,9 +1281,9 @@ (define_expand "movmemdi"
;; Operands 1 and 3 are tied together by the final condition; so we allow
;; fairly lax checking on the second memory operation.
(define_insn "load_pairsi"
- [(set (match_operand:SI 0 "register_operand" "=r,*w")
+ [(set (match_operand:SI 0 "register_operand" "=r,w")
(match_operand:SI 1 "aarch64_mem_pair_operand" "Ump,Ump"))
- (set (match_operand:SI 2 "register_operand" "=r,*w")
+ (set (match_operand:SI 2 "register_operand" "=r,w")
(match_operand:SI 3 "memory_operand" "m,m"))]
"rtx_equal_p (XEXP (operands[3], 0),
plus_constant (Pmode,
@@ -1297,9 +1297,9 @@ (define_insn "load_pairsi"
)
(define_insn "load_pairdi"
- [(set (match_operand:DI 0 "register_operand" "=r,*w")
+ [(set (match_operand:DI 0 "register_operand" "=r,w")
(match_operand:DI 1 "aarch64_mem_pair_operand" "Ump,Ump"))
- (set (match_operand:DI 2 "register_operand" "=r,*w")
+ (set (match_operand:DI 2 "register_operand" "=r,w")
(match_operand:DI 3 "memory_operand" "m,m"))]
"rtx_equal_p (XEXP (operands[3], 0),
plus_constant (Pmode,
@@ -1317,9 +1317,9 @@ (define_insn "load_pairdi"
;; fairly lax checking on the second memory operation.
(define_insn "store_pairsi"
[(set (match_operand:SI 0 "aarch64_mem_pair_operand" "=Ump,Ump")
- (match_operand:SI 1 "aarch64_reg_or_zero" "rZ,*w"))
+ (match_operand:SI 1 "aarch64_reg_or_zero" "rZ,w"))
(set (match_operand:SI 2 "memory_operand" "=m,m")
- (match_operand:SI 3 "aarch64_reg_or_zero" "rZ,*w"))]
+ (match_operand:SI 3 "aarch64_reg_or_zero" "rZ,w"))]
"rtx_equal_p (XEXP (operands[2], 0),
plus_constant (Pmode,
XEXP (operands[0], 0),
@@ -1333,9 +1333,9 @@ (define_insn "store_pairsi"
(define_insn "store_pairdi"
[(set (match_operand:DI 0 "aarch64_mem_pair_operand" "=Ump,Ump")
- (match_operand:DI 1 "aarch64_reg_or_zero" "rZ,*w"))
+ (match_operand:DI 1 "aarch64_reg_or_zero" "rZ,w"))
(set (match_operand:DI 2 "memory_operand" "=m,m")
- (match_operand:DI 3 "aarch64_reg_or_zero" "rZ,*w"))]
+ (match_operand:DI 3 "aarch64_reg_or_zero" "rZ,w"))]
"rtx_equal_p (XEXP (operands[2], 0),
plus_constant (Pmode,
XEXP (operands[0], 0),
@@ -1350,9 +1350,9 @@ (define_insn "store_pairdi"
;; Operands 1 and 3 are tied together by the final condition; so we allow
;; fairly lax checking on the second memory operation.
(define_insn "load_pairsf"
- [(set (match_operand:SF 0 "register_operand" "=w,*r")
+ [(set (match_operand:SF 0 "register_operand" "=w,r")
(match_operand:SF 1 "aarch64_mem_pair_operand" "Ump,Ump"))
- (set (match_operand:SF 2 "register_operand" "=w,*r")
+ (set (match_operand:SF 2 "register_operand" "=w,r")
(match_operand:SF 3 "memory_operand" "m,m"))]
"rtx_equal_p (XEXP (operands[3], 0),
plus_constant (Pmode,
@@ -1366,9 +1366,9 @@ (define_insn "load_pairsf"
)
(define_insn "load_pairdf"
- [(set (match_operand:DF 0 "register_operand" "=w,*r")
+ [(set (match_operand:DF 0 "register_operand" "=w,r")
(match_operand:DF 1 "aarch64_mem_pair_operand" "Ump,Ump"))
- (set (match_operand:DF 2 "register_operand" "=w,*r")
+ (set (match_operand:DF 2 "register_operand" "=w,r")
(match_operand:DF 3 "memory_operand" "m,m"))]
"rtx_equal_p (XEXP (operands[3], 0),
plus_constant (Pmode,
@@ -1385,9 +1385,9 @@ (define_insn "load_pairdf"
;; fairly lax checking on the second memory operation.
(define_insn "store_pairsf"
[(set (match_operand:SF 0 "aarch64_mem_pair_operand" "=Ump,Ump")
- (match_operand:SF 1 "aarch64_reg_or_fp_zero" "w,*rY"))
+ (match_operand:SF 1 "aarch64_reg_or_fp_zero" "w,rY"))
(set (match_operand:SF 2 "memory_operand" "=m,m")
- (match_operand:SF 3 "aarch64_reg_or_fp_zero" "w,*rY"))]
+ (match_operand:SF 3 "aarch64_reg_or_fp_zero" "w,rY"))]
"rtx_equal_p (XEXP (operands[2], 0),
plus_constant (Pmode,
XEXP (operands[0], 0),
@@ -1401,9 +1401,9 @@ (define_insn "store_pairsf"
(define_insn "store_pairdf"
[(set (match_operand:DF 0 "aarch64_mem_pair_operand" "=Ump,Ump")
- (match_operand:DF 1 "aarch64_reg_or_fp_zero" "w,*rY"))
+ (match_operand:DF 1 "aarch64_reg_or_fp_zero" "w,rY"))
(set (match_operand:DF 2 "memory_operand" "=m,m")
- (match_operand:DF 3 "aarch64_reg_or_fp_zero" "w,*rY"))]
+ (match_operand:DF 3 "aarch64_reg_or_fp_zero" "w,rY"))]
"rtx_equal_p (XEXP (operands[2], 0),
plus_constant (Pmode,
XEXP (operands[0], 0),
@@ -1554,7 +1554,7 @@ (define_insn "*extend<SHORT:mode><GPI:mode>2_aarch64"
)
(define_insn "*zero_extend<SHORT:mode><GPI:mode>2_aarch64"
- [(set (match_operand:GPI 0 "register_operand" "=r,r,*w")
+ [(set (match_operand:GPI 0 "register_operand" "=r,r,w")
(zero_extend:GPI (match_operand:SHORT 1 "nonimmediate_operand"
"r,m,m")))]
""
"@
@@ -5088,7 +5088,7 @@ (define_insn "<optab>_trunc<fcvt_change_mode><GPI:mode>2"
(define_insn "<optab><fcvt_target><GPF:mode>2"
[(set (match_operand:GPF 0 "register_operand" "=w,w")
- (FLOATUORS:GPF (match_operand:<FCVT_TARGET> 1 "register_operand"
"w,r")))]
+ (FLOATUORS:GPF (match_operand:<FCVT_TARGET> 1 "register_operand"
"w,?r")))]
"TARGET_FLOAT"
"@
<su_optab>cvtf\t%<GPF:s>0, %<s>1
diff --git a/gcc/testsuite/gcc.target/aarch64/vfp-1.c
b/gcc/testsuite/gcc.target/aarch64/vfp-1.c
index
79c571402cc1c5e3a8b6c71a30edb230a101e1a0..02609bb52bafd43803be29cf15225568f7713434
100644
--- a/gcc/testsuite/gcc.target/aarch64/vfp-1.c
+++ b/gcc/testsuite/gcc.target/aarch64/vfp-1.c
@@ -32,7 +32,7 @@ void test_sf() {
/* { dg-final { scan-assembler "fsqrt\ts\[0-9\]*" } } */
f1 = sqrtf (f1);
/* cmpsf */
- /* { dg-final { scan-assembler "fcmp\ts\[0-9\]*" } } */
+ /* { dg-final { scan-assembler "fcmpe\ts\[0-9\]*" } } */
if (f1 < f2)
cond1 = 1;
else
@@ -64,7 +64,7 @@ void test_df() {
/* { dg-final { scan-assembler "fsqrt\td\[0-9\]*" } } */
d1 = sqrt (d1);
/* cmpdf */
- /* { dg-final { scan-assembler "fcmp\td\[0-9\]*" } } */
+ /* { dg-final { scan-assembler "fcmpe\td\[0-9\]*" } } */
if (d1 < d2)
cond1 = 1;
else
@@ -82,13 +82,13 @@ void test_convert () {
/* { dg-final { scan-assembler "fcvt\ts\[0-9\]*" } } */
f1 = d1;
/* fixsfsi2 */
- /* { dg-final { scan-assembler "fcvtzs\tw\[0-9\], s\[0-9\]*" } } */
+ /* { dg-final { scan-assembler "fcvtzs\ts\[0-9\], s\[0-9\]*" } } */
i1 = f1;
/* fixdfsi2 */
/* { dg-final { scan-assembler "fcvtzs\tw\[0-9\], d\[0-9\]*" } } */
i1 = d1;
/* fixunsfsi2 */
- /* { dg-final { scan-assembler "fcvtzu\tw\[0-9\], s\[0-9\]*" } } */
+ /* { dg-final { scan-assembler "fcvtzu\ts\[0-9\], s\[0-9\]*" } } */
u1 = f1;
/* fixunsdfsi2 */
/* { dg-final { scan-assembler "fcvtzu\tw\[0-9\], d\[0-9\]*" } } */
