On Mon, Jan 15, 2018 at 11:29:50AM -0600, Will Schmidt wrote:
> > How do these two differ? The xx variant can write all 64 VSR registers,
> > it needs different constraints (wa?). Can the two patterns be merged?
> > It doesn't need the TARGET_P8_VECTOR condition then: the constraints
> > will handle that. And actually it is a v2.06 insn (p7)?
>
>
> They differ in..
> TARGET_P8_VECTOR, versus TARGET_ALTIVEC
> xxmrghw %x0,%x1,%x2, versus vmrghw %0,%1,%2
>
> Not clear to me if they can be merged. I'm weak in my grasp of the
> constraints. I can dig into that, (and would accept additional hints
> too :-) )
>
> xxmrghw does show up in my book as V2.06.
>
>
> In full, for reference:
>
>
> (define_insn "altivec_xxmrghw_direct"
> [(set (match_operand:V4SI 0 "register_operand" "=v")
> (unspec:V4SI [(match_operand:V4SI 1 "register_operand" "v")
> (match_operand:V4SI 2 "register_operand" "v")]
> UNSPEC_VMRGH_DIRECT))]
> "TARGET_P8_VECTOR"
> "xxmrghw %x0,%x1,%x2"
> [(set_attr "type" "vecperm")])
>
> (define_insn "altivec_vmrghw_direct"
> [(set (match_operand:V4SI 0 "register_operand" "=v")
> (unspec:V4SI [(match_operand:V4SI 1 "register_operand" "v")
> (match_operand:V4SI 2 "register_operand" "v")]
> UNSPEC_VMRGH_DIRECT))]
> "TARGET_ALTIVEC"
> "vmrghw %0,%1,%2"
> [(set_attr "type" "vecperm")])
Something like
(define_insn "altivec_vmrghw_direct"
[(set (match_operand:V4SI 0 "register_operand" "=v,wa")
(unspec:V4SI [(match_operand:V4SI 1 "register_operand" "v,wa")
(match_operand:V4SI 2 "register_operand" "v,wa")]
UNSPEC_VMRGH_DIRECT))]
"TARGET_ALTIVEC"
"*
vmrghw %0,%1,%2
xxmrghw %x0,%x1,%x2"
[(set_attr "type" "vecperm")])
should work (but maybe the "vmrghw" name should be changed then, drop
the "v"? Not sure what we do elsewhere. Fine to postpone that, too).
(The "wa" constraint is not active unless there is VSX support, which
is exactly ISA 2.06 and up).
Segher
