On Thu, Jan 11, 2018 at 1:49 PM, Bin Cheng <bin.ch...@arm.com> wrote: > Hi, > As explained in comment of PR83695, outdated cached scev info could be > referred > by later interchange of outer loops in nest. This simple patch fixes ICE by > resetting cached scev info after interchange. It's expensive resetting all > scev > information but might not be a problem here given we only interchange in > limited > cases. > > Bootstrap and test on x86_64 and AArch64. Is it OK?
Ok. Richard. > Thanks, > bin > > 2018-01-11 Bin Cheng <bin.ch...@arm.com> > > PR tree-optimization/83695 > * gimple-loop-linterchange.cc > (tree_loop_interchange::interchange_loops): Call scev_reset_htab to > reset cached scev information after interchange. > (pass_linterchange::execute): Remove call to scev_reset_htab. > > gcc/testsuite > 2018-01-11 Bin Cheng <bin.ch...@arm.com> > > PR tree-optimization/83695 > * gcc.dg/tree-ssa/pr83695.c: New test.
