On Fri, 5 Jan 2018, Richard Earnshaw (lists) wrote:
> This is quite tricky. For ARM we have to have a speculated load.
Sorry, I don't follow. On ARM, it is surprising that CSEL-CSDB-LDR sequence
wouldn't work (applying CSEL to the address rather than loaded value), and
if it wouldn't, then ARM-specific lowering of the builtin can handle that
anyhow, right? (by spilling the pointer)
(on x86 the current Intel's recommendation is to emit LFENCE prior to the load)
Is the main issue expressing the CSEL condition in the source code? Perhaps it
is
possible to introduce
int guard = __builtin_nontransparent(predicate);
if (predicate)
foo = __builtin_load_no_speculate(&arr[addr], guard);
... or maybe even
if (predicate)
foo = arr[__builtin_loadspecbarrier(addr, guard)];
where internally __builtin_nontransparent is the same as
guard = predicate;
asm volatile("" : "+g"(guard));
although admittedly this is not perfect since it forces evaluation of 'guard'
before the branch.
Alexander
