On Thu, Dec 21, 2017 at 06:16:16PM +0000, Joseph Myers wrote: > On Fri, 17 Nov 2017, Michael Meissner wrote: > The architecture-independent changes are OK. However, I have a comment on > the target parts: > > > +(define_insn "round<mode>2" > > + [(set (match_operand:IEEE128 0 "altivec_register_operand" "=v") > > + (unspec:IEEE128 > > + [(match_operand:IEEE128 1 "altivec_register_operand" "v")] > > + UNSPEC_FRIN))] > > + "TARGET_FLOAT128_HW && FLOAT128_IEEE_P (<MODE>mode)" > > + "xsrqpi 0,%0,%1,3" > > + [(set_attr "type" "vecfloat") > > + (set_attr "size" "128")]) > > My reading of Power ISA 3.0B documentation is that 0,%0,%1,3 means round > in the mode specified by FPSCR and you need 0,%0,%1,0 for > round-to-nearest-away semantics which are what the round<mode>2 > instruction has (i.e., what you've written here is actually correct for > nearbyint<mode>2, and would be rint<mode>2 if xsrqpix were used instead).
Ah yes, the roundM2 insn is round-away-from-zero, so you are right. Tricky, from the name I assumed it would be "current rounding mode" :-/ Not that "frin" would make sense if that were true. Thanks! And thanks for all the reviews in general. Segher
