GCC Maintainers:
The following patch add support for the builtin:
vector signed int __builtin_altivec_vsumsws_be (vector signed int, vector
signed int)
The patch has been tested on
powerpc64le-unknown-linux-gnu (Power 8 LE),
powerpc64le-unknown-linux-gnu (Power 9 LE)
without regressions.
Please let me know if the following patch is acceptable. Thanks.
Carl Love
--------------------------------------------------------------------------
gcc/ChangeLog:
2017-11-08 Carl Love <c...@us.ibm.com>
* config/rs6000/rs6000-c.c (ALTIVEC_BUILTIN_VEC_SUMS): Add macro
expansion.
* config/rs6000/altivec.md (altivec_vsumsws_be): Add define_expand.
* config/rs6000/rs6000-builtin.def (VSUMSWS_BE): Add macro expansion.
gcc/testsuite/ChangeLog:
2017-11-08 Carl Love <c...@us.ibm.com>
* gcc.target/powerpc/builtin-vec-sums-be-int.c: New test file.
---
gcc/config/rs6000/altivec.md | 11 +++++++++++
gcc/config/rs6000/rs6000-builtin.def | 1 +
.../gcc.target/powerpc/builtin-vec-sums-be-int.c | 16 ++++++++++++++++
3 files changed, 28 insertions(+)
create mode 100644 gcc/testsuite/gcc.target/powerpc/builtin-vec-sums-be-int.c
diff --git a/gcc/config/rs6000/altivec.md b/gcc/config/rs6000/altivec.md
index 651f6c9..706001c 100644
--- a/gcc/config/rs6000/altivec.md
+++ b/gcc/config/rs6000/altivec.md
@@ -1905,6 +1905,17 @@
DONE;
})
+(define_expand "altivec_vsumsws_be"
+ [(use (match_operand:V4SI 0 "register_operand"))
+ (use (match_operand:V4SI 1 "register_operand"))
+ (use (match_operand:V4SI 2 "register_operand"))]
+ "TARGET_ALTIVEC"
+{
+ emit_insn (gen_altivec_vsumsws_direct (operands[0], operands[1],
+ operands[2]));
+ DONE;
+})
+
; FIXME: This can probably be expressed without an UNSPEC.
(define_insn "altivec_vsumsws_direct"
[(set (match_operand:V4SI 0 "register_operand" "=v")
diff --git a/gcc/config/rs6000/rs6000-builtin.def
b/gcc/config/rs6000/rs6000-builtin.def
index 9dddc11..6addfdc 100644
--- a/gcc/config/rs6000/rs6000-builtin.def
+++ b/gcc/config/rs6000/rs6000-builtin.def
@@ -1079,6 +1079,7 @@ BU_ALTIVEC_2 (VSUM4SBS, "vsum4sbs", CONST,
altivec_vsum4sbs)
BU_ALTIVEC_2 (VSUM4SHS, "vsum4shs", CONST,
altivec_vsum4shs)
BU_ALTIVEC_2 (VSUM2SWS, "vsum2sws", CONST,
altivec_vsum2sws)
BU_ALTIVEC_2 (VSUMSWS, "vsumsws", CONST, altivec_vsumsws)
+BU_ALTIVEC_2 (VSUMSWS_BE, "vsumsws_be", CONST, altivec_vsumsws_be)
BU_ALTIVEC_2 (VXOR, "vxor", CONST, xorv4si3)
BU_ALTIVEC_2 (COPYSIGN_V4SF, "copysignfp", CONST, vector_copysignv4sf3)
diff --git a/gcc/testsuite/gcc.target/powerpc/builtin-vec-sums-be-int.c
b/gcc/testsuite/gcc.target/powerpc/builtin-vec-sums-be-int.c
new file mode 100644
index 0000000..b4dfd06
--- /dev/null
+++ b/gcc/testsuite/gcc.target/powerpc/builtin-vec-sums-be-int.c
@@ -0,0 +1,16 @@
+/* Test for the __builtin_altivec_vsumsws_be() builtin.
+ It produces just the instruction vsumsws in LE and BE modes. */
+
+/* { dg-do compile } */
+/* { dg-require-effective-target powerpc_altivec_ok } */
+/* { dg-options "-maltivec -O2" } */
+
+#include <altivec.h>
+
+vector signed int
+test_vec_sums (vector signed int vsi2, vector signed int vsi3)
+{
+ return __builtin_altivec_vsumsws_be (vsi2, vsi3);
+}
+
+/* { dg-final { scan-assembler-times "vsumsws" 1 } } */
--
2.7.4
