Actually I did changes to add the new field for linux under ifdef __linux__.
> -----Original Message----- > From: Jeff Law [mailto:l...@redhat.com] > Sent: Tuesday, October 31, 2017 12:21 AM > To: Tsimbalist, Igor V <igor.v.tsimbal...@intel.com>; gcc- > patc...@gcc.gnu.org > Cc: trie...@redhat.com > Subject: Re: [PATCH 21/22] Enable building libitm with Intel CET > > On 10/12/2017 03:21 PM, Tsimbalist, Igor V wrote: > > Enable building libitm with Intel CET options. > > > > libitm/ > > * Makefile.in: Regenerate. > > * acinclude.m4: Add enable.m4 and cet.m4. > > * config/x86/sjlj.S > > (_ITM_beginTransaction): Save Shadow Stack pointer. > > (GTM_longjmp): Restore Shadow Stack pointer. > > * config/x86/target.h (struct gtm_jmpbuf): > > Add Shadow Stack pointer. > > * configure: Regenerate. > > * configure.ac: Set CET_FLAGS. Update XCFLAGS, libtool_VERSION. > > * testsuite/Makefile.in: Regenerate. > > > > * config/cet.m4: Define ENABLE_CET_COMPATIBILITY. Set > > enable_cet_compatibility. > > > Would it make sense to avoid having different sizes of gtm_jmpbuf by > simply having the ssp slot always defined, even if we're not using it? Yes, it make sense. We can do it for x86 configuration. In that case the conditional code will be limited to Shadow Stack pointer read/write. > Along the same lines, would it make sense to have that field at the end > of the structure so that the amount of conditional code in in sjlj.S is > minimized (ie, all the offests are the same, so in the CET case you just > have a single extra store). The comments says the buffer is specially located in such a way that eip/rip field overlap with a return address on the stack. That means the field can be added anywhere before eip/rip and in turn the offsets will change. I will re-implement the fixes with adding the new field for x86 only. Igor > > Jeff
