Ping. There was discussion of larger fixes for this including a type promotion pass but this patch seems small, safe, and in line with other platforms (like arm32).
Steve Ellcey sell...@cavium.com On Thu, 2017-09-14 at 11:43 -0700, Steve Ellcey wrote: > On Thu, 2017-09-14 at 11:53 -0600, Jeff Law wrote: > > > > > > > > And I think that's starting to zero in on the problem -- > > WORD_REGISTER_OPERATIONS is zero on aarch64 as you don't get > > extension > > to word_mode for W form registers. > > > > I wonder if what needs to happen is somehow look to extend that > > code > > somehow so that combine and friends know that the value is zero > > extended > > to 32 bits, even if it's not extended to word_mode. > > > > Jeff > This might be a good long term direction to move but in the mean time > it sure does seem a lot easier to just generate a subreg. Here is a > patch that does that, it passes bootstrap and has no regressions and > fixes the bug in question (and most likely improves other code as > well). > > The "LOAD_EXTEND_OP (<MODE>mode) == ZERO_EXTEND" part of the if > statement is not really necessary since we know this is true on > aarch64 > but I thought it helped make it clear what we were doing and the > compiler should optimize it away anyway. > > OK to checkin this fix while we consider longer term options? > > Steve Ellcey > sell...@cavium.com > > > 2017-09-14 Steve Ellcey <sell...@cavium.com> > > PR target/77729 > * config/aarch64/aarch64.md (mov<mode>): Generate subreg for > short loads to reflect that upper bits are zeroed out on load. > > > 2017-09-14 Steve Ellcey <sell...@cavium.com> > > * gcc.target/aarch64/pr77729.c: New test. >
