From 8fb6e5f3bb98c9a6f52a27bc2e4e3c085736bd10 Mon Sep 17 00:00:00 2001 From: "julia.koval" Date: Mon, 20 Feb 2017 14:25:53 +0300 Subject: [PATCH 2/4] GF2P8AFFINEINVQB instruction --- gcc/config.gcc | 4 +- gcc/config/i386/gfniintrin.h | 229 +++++++++++++++++++++ gcc/config/i386/i386-builtin-types.def | 6 + gcc/config/i386/i386-builtin.def | 7 + gcc/config/i386/i386.c | 8 + gcc/config/i386/immintrin.h | 2 + gcc/config/i386/sse.md | 23 +++ gcc/testsuite/gcc.target/i386/avx-1.c | 10 + gcc/testsuite/gcc.target/i386/avx512-check.h | 3 + .../gcc.target/i386/avx512f-gf2p8affineinvqb-2.c | 74 +++++++ .../gcc.target/i386/avx512vl-gf2p8affineinvqb-2.c | 17 ++ gcc/testsuite/gcc.target/i386/gfni-1.c | 18 ++ gcc/testsuite/gcc.target/i386/gfni-2.c | 27 +++ gcc/testsuite/gcc.target/i386/gfni-3.c | 17 ++ gcc/testsuite/gcc.target/i386/gfni-4.c | 14 ++ gcc/testsuite/gcc.target/i386/i386.exp | 15 ++ gcc/testsuite/gcc.target/i386/sse-13.c | 8 + gcc/testsuite/gcc.target/i386/sse-23.c | 8 + 18 files changed, 488 insertions(+), 2 deletions(-) create mode 100644 gcc/config/i386/gfniintrin.h create mode 100644 gcc/testsuite/gcc.target/i386/avx512f-gf2p8affineinvqb-2.c create mode 100644 gcc/testsuite/gcc.target/i386/avx512vl-gf2p8affineinvqb-2.c create mode 100644 gcc/testsuite/gcc.target/i386/gfni-1.c create mode 100644 gcc/testsuite/gcc.target/i386/gfni-2.c create mode 100644 gcc/testsuite/gcc.target/i386/gfni-3.c create mode 100644 gcc/testsuite/gcc.target/i386/gfni-4.c diff --git a/gcc/config.gcc b/gcc/config.gcc index 2270239..25e50d7 100644 --- a/gcc/config.gcc +++ b/gcc/config.gcc @@ -378,7 +378,7 @@ i[34567]86-*-*) avx512ifmaintrin.h avx512ifmavlintrin.h avx512vbmiintrin.h avx512vbmivlintrin.h avx5124fmapsintrin.h avx5124vnniwintrin.h avx512vpopcntdqintrin.h clwbintrin.h mwaitxintrin.h - clzerointrin.h pkuintrin.h sgxintrin.h" + clzerointrin.h pkuintrin.h sgxintrin.h gfniintrin.h" ;; x86_64-*-*) cpu_type=i386 @@ -402,7 +402,7 @@ x86_64-*-*) avx512ifmaintrin.h avx512ifmavlintrin.h avx512vbmiintrin.h avx512vbmivlintrin.h avx5124fmapsintrin.h avx5124vnniwintrin.h avx512vpopcntdqintrin.h clwbintrin.h mwaitxintrin.h - clzerointrin.h pkuintrin.h sgxintrin.h" + clzerointrin.h pkuintrin.h sgxintrin.h gfniintrin.h" ;; ia64-*-*) extra_headers=ia64intrin.h diff --git a/gcc/config/i386/gfniintrin.h b/gcc/config/i386/gfniintrin.h new file mode 100644 index 0000000..a42c205 --- /dev/null +++ b/gcc/config/i386/gfniintrin.h @@ -0,0 +1,229 @@ +/* Copyright (C) 2014-2017 Free Software Foundation, Inc. + + This file is part of GCC. + + GCC is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3, or (at your option) + any later version. + + GCC is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + Under Section 7 of GPL version 3, you are granted additional + permissions described in the GCC Runtime Library Exception, version + 3.1, as published by the Free Software Foundation. + + You should have received a copy of the GNU General Public License and + a copy of the GCC Runtime Library Exception along with this program; + see the files COPYING3 and COPYING.RUNTIME respectively. If not, see + . */ + +#ifndef _IMMINTRIN_H_INCLUDED +#error "Never use directly; include instead." +#endif + +#ifndef _GFNIINTRIN_H_INCLUDED +#define _GFNIINTRIN_H_INCLUDED + +#ifndef __GFNI__ +#pragma GCC push_options +#pragma GCC target("gfni") +#define __DISABLE_GFNI__ +#endif /* __GFNI__ */ + +#ifdef __OPTIMIZE__ +extern __inline __m128i +__attribute__((__gnu_inline__, __always_inline__, __artificial__)) +_mm_gf2p8affineinv_epi64_epi8 (__m128i __A, __m128i __B, const int __C) +{ + return (__m128i) __builtin_ia32_vgf2p8affineinvqb_v16qi ((__v16qi) __A, + (__v16qi) __B, + __C); +} +#else +#define _mm_gf2p8affineinv_epi64_epi8(A, B, C) \ + ((__m128i) __builtin_ia32_vgf2p8affineinvqb_v16qi((__v16qi)(__m128i)(A), \ + (__v16qi)(__m128i)(B), (int)(C))) +#endif + +#ifdef __DISABLE_GFNI__ +#undef __DISABLE_GFNI__ +#pragma GCC pop_options +#endif /* __DISABLE_GFNI__ */ + +#if !defined(__GFNI__) || !defined(__AVX__) +#pragma GCC push_options +#pragma GCC target("gfni,avx") +#define __DISABLE_GFNIAVX__ +#endif /* __GFNIAVX__ */ + +#ifdef __OPTIMIZE__ +extern __inline __m256i +__attribute__((__gnu_inline__, __always_inline__, __artificial__)) +_mm256_gf2p8affineinv_epi64_epi8 (__m256i __A, __m256i __B, const int __C) +{ + return (__m256i) __builtin_ia32_vgf2p8affineinvqb_v32qi ((__v32qi) __A, + (__v32qi) __B, + __C); +} +#else +#define _mm256_gf2p8affineinv_epi64_epi8(A, B, C) \ + ((__m256i) __builtin_ia32_vgf2p8affineinvqb_v32qi((__v32qi)(__m256i)(A), \ + (__v32qi)(__m256i)(B), \ + (int)(C))) +#endif + +#ifdef __DISABLE_GFNIAVX__ +#undef __DISABLE_GFNIAVX__ +#pragma GCC pop_options +#endif /* __GFNIAVX__ */ + +#if !defined(__GFNI__) || !defined(__AVX512VL__) +#pragma GCC push_options +#pragma GCC target("gfni,avx512vl") +#define __DISABLE_GFNIAVX512VL__ +#endif /* __GFNIAVX512VL__ */ + +#ifdef __OPTIMIZE__ +extern __inline __m128i +__attribute__((__gnu_inline__, __always_inline__, __artificial__)) +_mm_mask_gf2p8affineinv_epi64_epi8 (__m128i __A, __mmask16 __B, __m128i __C, + __m128i __D, const int __E) +{ + return (__m128i) __builtin_ia32_vgf2p8affineinvqb_v16qi_mask ((__v16qi) __C, + (__v16qi) __D, + __E, + (__v16qi)__A, + __B); +} + +extern __inline __m128i +__attribute__((__gnu_inline__, __always_inline__, __artificial__)) +_mm_maskz_gf2p8affineinv_epi64_epi8 (__mmask16 __A, __m128i __B, __m128i __C, + const int __D) +{ + return (__m128i) __builtin_ia32_vgf2p8affineinvqb_v16qi_mask ((__v16qi) __B, + (__v16qi) __C, __D, + (__v16qi) _mm_setzero_si128 (), + __A); +} +#else +#define _mm_mask_gf2p8affineinv_epi64_epi8(A, B, C, D, E) \ + ((__m128i) __builtin_ia32_vgf2p8affineinvqb_v16qi_mask( \ + (__v16qi)(__m128i)(C), (__v16qi)(__m128i)(D), \ + (int)(E), (__v16qi)(__m128i)(A), (__mmask16)(B))) +#define _mm_maskz_gf2p8affineinv_epi64_epi8(A, B, C, D) \ + ((__m128i) __builtin_ia32_vgf2p8affineinvqb_v16qi_mask( \ + (__v16qi)(__m128i)(B), (__v16qi)(__m128i)(C), \ + (int)(D), (__v16qi)(__m128i) _mm_setzero_si128 (), \ + (__mmask16)(A))) +#endif + +#ifdef __DISABLE_GFNIAVX512VL__ +#undef __DISABLE_GFNIAVX512VL__ +#pragma GCC pop_options +#endif /* __GFNIAVX512VL__ */ + +#if !defined(__GFNI__) || !defined(__AVX512VL__) || !defined(__AVX512BW__) +#pragma GCC push_options +#pragma GCC target("gfni,avx512vl,avx512bw") +#define __DISABLE_GFNIAVX512VLBW__ +#endif /* __GFNIAVX512VLBW__ */ + +#ifdef __OPTIMIZE__ +extern __inline __m256i +__attribute__((__gnu_inline__, __always_inline__, __artificial__)) +_mm256_mask_gf2p8affineinv_epi64_epi8 (__m256i __A, __mmask32 __B, + __m256i __C, __m256i __D, const int __E) +{ + return (__m256i) __builtin_ia32_vgf2p8affineinvqb_v32qi_mask ((__v32qi) __C, + (__v32qi) __D, + __E, + (__v32qi)__A, + __B); +} + +extern __inline __m256i +__attribute__((__gnu_inline__, __always_inline__, __artificial__)) +_mm256_maskz_gf2p8affineinv_epi64_epi8 (__mmask32 __A, __m256i __B, + __m256i __C, const int __D) +{ + return (__m256i) __builtin_ia32_vgf2p8affineinvqb_v32qi_mask ((__v32qi) __B, + (__v32qi) __C, __D, + (__v32qi) _mm256_setzero_si256 (), __A); +} +#else +#define _mm256_mask_gf2p8affineinv_epi64_epi8(A, B, C, D, E) \ + ((__m256i) __builtin_ia32_vgf2p8affineinvqb_v32qi_mask( \ + (__v32qi)(__m256i)(C), (__v32qi)(__m256i)(D), (int)(E), \ + (__v32qi)(__m256i)(A), (__mmask32)(B))) +#define _mm256_maskz_gf2p8affineinv_epi64_epi8(A, B, C, D) \ + ((__m256i) __builtin_ia32_vgf2p8affineinvqb_v32qi_mask( \ + (__v32qi)(__m256i)(B), (__v32qi)(__m256i)(C), (int)(D), \ + (__v32qi)(__m256i) _mm256_setzero_si256 (), (__mmask32)(A))) +#endif + +#ifdef __DISABLE_GFNIAVX512VLBW__ +#undef __DISABLE_GFNIAVX512VLBW__ +#pragma GCC pop_options +#endif /* __GFNIAVX512VLBW__ */ + +#if !defined(__GFNI__) || !defined(__AVX512F__) || !defined(__AVX512BW__) +#pragma GCC push_options +#pragma GCC target("gfni,avx512f,avx512bw") +#define __DISABLE_GFNIAVX512FBW__ +#endif /* __GFNIAVX512FBW__ */ + +#ifdef __OPTIMIZE__ +extern __inline __m512i +__attribute__((__gnu_inline__, __always_inline__, __artificial__)) +_mm512_mask_gf2p8affineinv_epi64_epi8 (__m512i __A, __mmask64 __B, __m512i __C, + __m512i __D, const int __E) +{ + return (__m512i) __builtin_ia32_vgf2p8affineinvqb_v64qi_mask ((__v64qi) __C, + (__v64qi) __D, + __E, + (__v64qi)__A, + __B); +} + +extern __inline __m512i +__attribute__((__gnu_inline__, __always_inline__, __artificial__)) +_mm512_maskz_gf2p8affineinv_epi64_epi8 (__mmask64 __A, __m512i __B, + __m512i __C, const int __D) +{ + return (__m512i) __builtin_ia32_vgf2p8affineinvqb_v64qi_mask ((__v64qi) __B, + (__v64qi) __C, __D, + (__v64qi) _mm512_setzero_si512 (), __A); +} + +extern __inline __m512i +__attribute__((__gnu_inline__, __always_inline__, __artificial__)) +_mm512_gf2p8affineinv_epi64_epi8 (__m512i __A, __m512i __B, const int __C) +{ + return (__m512i) __builtin_ia32_vgf2p8affineinvqb_v64qi ((__v64qi) __A, + (__v64qi) __B, __C); +} +#else +#define _mm512_mask_gf2p8affineinv_epi64_epi8(A, B, C, D, E) \ + ((__m512i) __builtin_ia32_vgf2p8affineinvqb_v64qi_mask( \ + (__v64qi)(__m512i)(C), (__v64qi)(__m512i)(D), (int)(E), \ + (__v64qi)(__m512i)(A), (__mmask64)(B))) +#define _mm512_maskz_gf2p8affineinv_epi64_epi8(A, B, C, D) \ + ((__m512i) __builtin_ia32_vgf2p8affineinvqb_v64qi_mask( \ + (__v64qi)(__m512i)(B), (__v64qi)(__m512i)(C), (int)(D), \ + (__v64qi)(__m512i) _mm512_setzero_si512 (), (__mmask64)(A))) +#define _mm512_gf2p8affineinv_epi64_epi8(A, B, C) \ + ((__m512i) __builtin_ia32_vgf2p8affineinvqb_v64qi ( \ + (__v64qi)(__m512i)(A), (__v64qi)(__m512i)(B), (int)(C))) +#endif + +#ifdef __DISABLE_GFNIAVX512FBW__ +#undef __DISABLE_GFNIAVX512FBW__ +#pragma GCC pop_options +#endif /* __GFNIAVX512FBW__ */ + +#endif /* _GFNIINTRIN_H_INCLUDED */ diff --git a/gcc/config/i386/i386-builtin-types.def b/gcc/config/i386/i386-builtin-types.def index 8d584db..f4508f4 100644 --- a/gcc/config/i386/i386-builtin-types.def +++ b/gcc/config/i386/i386-builtin-types.def @@ -1210,3 +1210,9 @@ DEF_FUNCTION_TYPE (BND, BND, BND) DEF_FUNCTION_TYPE (PVOID, PCVOID, BND, ULONG) DEF_FUNCTION_TYPE (ULONG, VOID) DEF_FUNCTION_TYPE (PVOID, BND) + +#GFNI builtins +DEF_FUNCTION_TYPE (V64QI, V64QI, V64QI, INT) +DEF_FUNCTION_TYPE (V64QI, V64QI, V64QI, INT, V64QI, UDI) +DEF_FUNCTION_TYPE (V32QI, V32QI, V32QI, INT, V32QI, USI) +DEF_FUNCTION_TYPE (V16QI, V16QI, V16QI, INT, V16QI, UHI) diff --git a/gcc/config/i386/i386-builtin.def b/gcc/config/i386/i386-builtin.def index 0d5d5b7..24d057d 100644 --- a/gcc/config/i386/i386-builtin.def +++ b/gcc/config/i386/i386-builtin.def @@ -2589,6 +2589,13 @@ BDESC (OPTION_MASK_ISA_AVX512VPOPCNTDQ, CODE_FOR_vpopcountv8di_mask, "__builtin_ /* RDPID */ BDESC (OPTION_MASK_ISA_RDPID, CODE_FOR_rdpid, "__builtin_ia32_rdpid", IX86_BUILTIN_RDPID, UNKNOWN, (int) UNSIGNED_FTYPE_VOID) +/* GFNI */ +BDESC (OPTION_MASK_ISA_GFNI, CODE_FOR_vgf2p8affineinvqb_v64qi, "__builtin_ia32_vgf2p8affineinvqb_v64qi", IX86_BUILTIN_VGF2P8AFFINEINVQB512, UNKNOWN, (int) V64QI_FTYPE_V64QI_V64QI_INT) +BDESC (OPTION_MASK_ISA_GFNI | OPTION_MASK_ISA_AVX512BW, CODE_FOR_vgf2p8affineinvqb_v64qi_mask, "__builtin_ia32_vgf2p8affineinvqb_v64qi_mask", IX86_BUILTIN_VGF2P8AFFINEINVQB512MASK, UNKNOWN, (int) V64QI_FTYPE_V64QI_V64QI_INT_V64QI_UDI) +BDESC (OPTION_MASK_ISA_GFNI, CODE_FOR_vgf2p8affineinvqb_v32qi, "__builtin_ia32_vgf2p8affineinvqb_v32qi", IX86_BUILTIN_VGF2P8AFFINEINVQB256, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI_INT) +BDESC (OPTION_MASK_ISA_GFNI | OPTION_MASK_ISA_AVX512BW, CODE_FOR_vgf2p8affineinvqb_v32qi_mask, "__builtin_ia32_vgf2p8affineinvqb_v32qi_mask", IX86_BUILTIN_VGF2P8AFFINEINVQB256MASK, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI_INT_V32QI_USI) +BDESC (OPTION_MASK_ISA_GFNI, CODE_FOR_vgf2p8affineinvqb_v16qi, "__builtin_ia32_vgf2p8affineinvqb_v16qi", IX86_BUILTIN_VGF2P8AFFINEINVQB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI_INT) +BDESC (OPTION_MASK_ISA_GFNI | OPTION_MASK_ISA_AVX512BW, CODE_FOR_vgf2p8affineinvqb_v16qi_mask, "__builtin_ia32_vgf2p8affineinvqb_v16qi_mask", IX86_BUILTIN_VGF2P8AFFINEINVQB128MASK, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI_INT_V16QI_UHI) BDESC_END (ARGS2, MPX) /* Builtins for MPX. */ diff --git a/gcc/config/i386/i386.c b/gcc/config/i386/i386.c index eaa98cd..5a192e4 100644 --- a/gcc/config/i386/i386.c +++ b/gcc/config/i386/i386.c @@ -33420,6 +33420,7 @@ ix86_expand_args_builtin (const struct builtin_description *d, case UQI_FTYPE_V4SF_V4SF_INT: case UHI_FTYPE_V16SI_V16SI_INT: case UHI_FTYPE_V16SF_V16SF_INT: + case V64QI_FTYPE_V64QI_V64QI_INT: nargs = 3; nargs_constant = 1; break; @@ -33647,6 +33648,13 @@ ix86_expand_args_builtin (const struct builtin_description *d, mask_pos = 1; nargs_constant = 1; break; + case V64QI_FTYPE_V64QI_V64QI_INT_V64QI_UDI: + case V32QI_FTYPE_V32QI_V32QI_INT_V32QI_USI: + case V16QI_FTYPE_V16QI_V16QI_INT_V16QI_UHI: + nargs = 5; + mask_pos = 1; + nargs_constant = 2; + break; default: gcc_unreachable (); diff --git a/gcc/config/i386/immintrin.h b/gcc/config/i386/immintrin.h index b52f58e..3169f6f 100644 --- a/gcc/config/i386/immintrin.h +++ b/gcc/config/i386/immintrin.h @@ -90,6 +90,8 @@ #include +#include + #ifndef __RDRND__ #pragma GCC push_options #pragma GCC target("rdrnd") diff --git a/gcc/config/i386/sse.md b/gcc/config/i386/sse.md index 0c26bd1..3199f19 100644 --- a/gcc/config/i386/sse.md +++ b/gcc/config/i386/sse.md @@ -157,6 +157,9 @@ UNSPEC_VP4FNMADD UNSPEC_VP4DPWSSD UNSPEC_VP4DPWSSDS + + ;; For GFNI support + UNSPEC_GF2P8AFFINEINV ]) (define_c_enum "unspecv" [ @@ -325,6 +328,9 @@ (define_mode_iterator VI1_AVX512 [(V64QI "TARGET_AVX512BW") (V32QI "TARGET_AVX2") V16QI]) +(define_mode_iterator VI1_AVX512F + [(V64QI "TARGET_AVX512F") (V32QI "TARGET_AVX") V16QI]) + (define_mode_iterator VI2_AVX2 [(V32HI "TARGET_AVX512BW") (V16HI "TARGET_AVX2") V8HI]) @@ -20165,3 +20171,20 @@ ])] "TARGET_SSE && TARGET_64BIT" "jmp\t%P1") + +(define_insn "vgf2p8affineinvqb_" + [(set (match_operand:VI1_AVX512F 0 "register_operand" "=x,x,v") + (unspec:VI1_AVX512F [(match_operand:VI1_AVX512F 1 "register_operand" "%0,x,v") + (match_operand:VI1_AVX512F 2 "nonimmediate_operand" "xBm,xm,vm") + (match_operand:QI 3 "const_0_to_255_operand" "n,n,n")] + UNSPEC_GF2P8AFFINEINV))] + "TARGET_GFNI" + "@ + gf2p8affineinvqb\t{%3, %2, %0| %0, %2, %3} + vgf2p8affineinvqb\t{%3, %2, %1, %0| %0, %1, %2, %3} + vgf2p8affineinvqb\t{%3, %2, %1, %0| %0, %1, %2, %3}" + [(set_attr "isa" "noavx,avx,avx512bw") + (set_attr "prefix_data16" "1,*,*") + (set_attr "prefix_extra" "1") + (set_attr "prefix" "orig,maybe_evex,evex") + (set_attr "mode" "")]) diff --git a/gcc/testsuite/gcc.target/i386/avx-1.c b/gcc/testsuite/gcc.target/i386/avx-1.c index 085ba81..67dea5b 100644 --- a/gcc/testsuite/gcc.target/i386/avx-1.c +++ b/gcc/testsuite/gcc.target/i386/avx-1.c @@ -603,6 +603,16 @@ #define __builtin_ia32_extracti64x2_256_mask(A, E, C, D) __builtin_ia32_extracti64x2_256_mask(A, 1, C, D) #define __builtin_ia32_extractf64x2_256_mask(A, E, C, D) __builtin_ia32_extractf64x2_256_mask(A, 1, C, D) +/* gfniintrin.h */ +#define __builtin_ia32_vgf2p8affineinvqb_v16qi(A, B, C) __builtin_ia32_vgf2p8affineinvqb_v16qi(A, B, 1) +#define __builtin_ia32_vgf2p8affineinvqb_v32qi(A, B, C) __builtin_ia32_vgf2p8affineinvqb_v32qi(A, B, 1) +#define __builtin_ia32_vgf2p8affineinvqb_v64qi(A, B, C) __builtin_ia32_vgf2p8affineinvqb_v64qi(A, B, 1) +#define __builtin_ia32_vgf2p8affineinvqb_v16qi_mask(A, B, C, D, E) __builtin_ia32_vgf2p8affineinvqb_v16qi_mask(A, B, 1, D, E) +#define __builtin_ia32_vgf2p8affineinvqb_v32qi_mask(A, B, C, D, E) __builtin_ia32_vgf2p8affineinvqb_v32qi_mask(A, B, 1, D, E) +#define __builtin_ia32_vgf2p8affineinvqb_v64qi_mask(A, B, C, D, E) __builtin_ia32_vgf2p8affineinvqb_v64qi_mask(A, B, 1, D, E) + + + #include #include #include diff --git a/gcc/testsuite/gcc.target/i386/avx512-check.h b/gcc/testsuite/gcc.target/i386/avx512-check.h index 9693fa4..9390c1a 100644 --- a/gcc/testsuite/gcc.target/i386/avx512-check.h +++ b/gcc/testsuite/gcc.target/i386/avx512-check.h @@ -75,6 +75,9 @@ main () #ifdef AVX512VPOPCNTDQ && (ecx & bit_AVX512VPOPCNTDQ) #endif +#ifdef GFNI + && (ecx & bit_GFNI) +#endif && avx512f_os_support ()) { DO_TEST (); diff --git a/gcc/testsuite/gcc.target/i386/avx512f-gf2p8affineinvqb-2.c b/gcc/testsuite/gcc.target/i386/avx512f-gf2p8affineinvqb-2.c new file mode 100644 index 0000000..af4839f --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/avx512f-gf2p8affineinvqb-2.c @@ -0,0 +1,74 @@ +/* { dg-do run } */ +/* { dg-options "-O2 -mavx512f -mgfni -mavx512bw" } */ +/* { dg-require-effective-target avx512f } */ +/* { dg-require-effective-target gfni } */ + +#define AVX512F + +#define GFNI +#include "avx512f-helper.h" + +#define SIZE (AVX512F_LEN / 8) + +#include "avx512f-mask-type.h" +#include + +static void +CALC (unsigned char *r, unsigned char *s1, unsigned char *s2, unsigned char imm) +{ + for (int a = 0; a < SIZE/8; a++) + { + for (int val = 0; val < 8; val++) + { + unsigned char result = 0; + for (int bit = 0; bit < 8; bit++) + { + unsigned char temp = s1[a*8 + val] & s2[a*8 + bit]; + unsigned char parity = __popcntd(temp); + if (parity % 2) + result |= (1 << (8 - bit - 1)); + } + r[a*8 + val] = result ^ imm; + } + } +} + +void +TEST (void) +{ + int i; + UNION_TYPE (AVX512F_LEN, i_b) res1, res2, res3, src1, src2; + MASK_TYPE mask = MASK_VALUE; + char res_ref[SIZE]; + unsigned char imm = 0; + + for (i = 0; i < SIZE; i++) + { + src1.a[i] = i %2 ; // gfni inverse of 1 and 0 are 1 and 0 + src2.a[i] = 1; + } + + for (i = 0; i < SIZE; i++) + { + res1.a[i] = DEFAULT_VALUE; + res2.a[i] = DEFAULT_VALUE; + res3.a[i] = DEFAULT_VALUE; + } + + CALC (res_ref, src1.a, src2.a, imm); + + res1.x = INTRINSIC (_gf2p8affineinv_epi64_epi8) (src1.x, src2.x, imm); + res2.x = INTRINSIC (_mask_gf2p8affineinv_epi64_epi8) (res2.x, mask, src1.x, src2.x, imm); + res3.x = INTRINSIC (_maskz_gf2p8affineinv_epi64_epi8) (mask, src1.x, src2.x, imm); + + if (UNION_CHECK (AVX512F_LEN, i_b) (res1, res_ref)) + abort (); + + MASK_MERGE (i_b) (res_ref, mask, SIZE); + if (UNION_CHECK (AVX512F_LEN, i_b) (res2, res_ref)) + abort (); + + MASK_ZERO (i_b) (res_ref, mask, SIZE); + if (UNION_CHECK (AVX512F_LEN, i_b) (res3, res_ref)) + abort (); +} diff --git a/gcc/testsuite/gcc.target/i386/avx512vl-gf2p8affineinvqb-2.c b/gcc/testsuite/gcc.target/i386/avx512vl-gf2p8affineinvqb-2.c new file mode 100644 index 0000000..fa54526 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/avx512vl-gf2p8affineinvqb-2.c @@ -0,0 +1,17 @@ +/* { dg-do run } */ +/* { dg-options "-O2 -mavx512bw -mavx512vl -mgfni" } */ +/* { dg-require-effective-target avx512vl } */ +/* { dg-require-effective-target avx512bw } */ +/* { dg-require-effective-target gfni } */ + +#define AVX512VL +#define AVX512F_LEN 256 +#define AVX512F_LEN_HALF 128 +#include "avx512f-gf2p8affineinvqb-2.c" + +#undef AVX512F_LEN +#undef AVX512F_LEN_HALF + +#define AVX512F_LEN 128 +#define AVX512F_LEN_HALF 128 +#include "avx512f-gf2p8affineinvqb-2.c" diff --git a/gcc/testsuite/gcc.target/i386/gfni-1.c b/gcc/testsuite/gcc.target/i386/gfni-1.c new file mode 100644 index 0000000..5e22c9e --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/gfni-1.c @@ -0,0 +1,18 @@ +/* { dg-do compile } */ +/* { dg-options "-mgfni -mavx512bw -mavx512f -O2" } */ +/* { dg-final { scan-assembler-times "vgf2p8affineinvqb\[ \\t\]+\[^\{\n\]*\\\$3\[^\n\r]*%zmm\[0-9\]+\[^\n\r]*%zmm\[0-9\]+\[^\n\r]*%zmm\[0-9\]+(?:\n|\[ \\t\]+#)" 1 } } */ +/* { dg-final { scan-assembler-times "vgf2p8affineinvqb\[ \\t\]+\[^\{\n\]*\\\$3\[^\n\r]*%zmm\[0-9\]+\[^\\n\\r]*%zmm\[0-9\]+\[^\\n\\r\]*%zmm\[0-9\]+\{%k\[1-7\]\}(?:\n|\[ \\t\]+#)" 1 } } */ +/* { dg-final { scan-assembler-times "vgf2p8affineinvqb\[ \\t\]+\[^\{\n\]*\\\$3\[^\n\r]*%zmm\[0-9\]+\[^\\n\\r]*%zmm\[0-9\]+\[^\\n\\r\]*%zmm\[0-9\]+\{%k\[1-7\]\}\{z\}(?:\n|\[ \\t\]+#)" 1 } } */ + +#include + +volatile __m512i x1, x2; +volatile __mmask64 m64; + +void extern +avx512vl_test (void) +{ + x1 = _mm512_gf2p8affineinv_epi64_epi8(x1, x2, 3); + x1 = _mm512_mask_gf2p8affineinv_epi64_epi8(x1, m64, x2, x1, 3); + x1 = _mm512_maskz_gf2p8affineinv_epi64_epi8(m64, x1, x2, 3); +} diff --git a/gcc/testsuite/gcc.target/i386/gfni-2.c b/gcc/testsuite/gcc.target/i386/gfni-2.c new file mode 100644 index 0000000..4d1f151 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/gfni-2.c @@ -0,0 +1,27 @@ +/* { dg-do compile } */ +/* { dg-options "-mgfni -mavx512bw -mavx512vl -O2" } */ +/* { dg-final { scan-assembler-times "vgf2p8affineinvqb\[ \\t\]+\[^\{\n\]*\\\$3\[^\n\r]*%ymm\[0-9\]+\[^\n\r]*%ymm\[0-9\]+\[^\n\r]*%ymm\[0-9\]+(?:\n|\[ \\t\]+#)" 1 } } */ +/* { dg-final { scan-assembler-times "vgf2p8affineinvqb\[ \\t\]+\[^\{\n\]*\\\$3\[^\n\r]*%ymm\[0-9\]+\[^\\n\\r]*%ymm\[0-9\]+\[^\\n\\r\]*%ymm\[0-9\]+\{%k\[1-7\]\}(?:\n|\[ \\t\]+#)" 1 } } */ +/* { dg-final { scan-assembler-times "vgf2p8affineinvqb\[ \\t\]+\[^\{\n\]*\\\$3\[^\n\r]*%ymm\[0-9\]+\[^\\n\\r]*%ymm\[0-9\]+\[^\\n\\r\]*%ymm\[0-9\]+\{%k\[1-7\]\}\{z\}(?:\n|\[ \\t\]+#)" 1 } } */ +/* { dg-final { scan-assembler-times "vgf2p8affineinvqb\[ \\t\]+\[^\{\n\]*\\\$3\[^\n\r]*%xmm\[0-9\]+\[^\n\r]*%xmm\[0-9\]+\[^\n\r]*%xmm\[0-9\]+(?:\n|\[ \\t\]+#)" 1 } } */ +/* { dg-final { scan-assembler-times "vgf2p8affineinvqb\[ \\t\]+\[^\{\n\]*\\\$3\[^\n\r]*%xmm\[0-9\]+\[^\\n\\r]*%xmm\[0-9\]+\[^\\n\\r\]*%xmm\[0-9\]+\{%k\[1-7\]\}(?:\n|\[ \\t\]+#)" 1 } } */ +/* { dg-final { scan-assembler-times "vgf2p8affineinvqb\[ \\t\]+\[^\{\n\]*\\\$3\[^\n\r]*%xmm\[0-9\]+\[^\\n\\r]*%xmm\[0-9\]+\[^\\n\\r\]*%xmm\[0-9\]+\{%k\[1-7\]\}\{z\}(?:\n|\[ \\t\]+#)" 1 } } */ + +#include + +int *p; +volatile __m256i x3, x4; +volatile __m128i x5, x6; +volatile __mmask32 m32; +volatile __mmask16 m16; + +void extern +avx512vl_test (void) +{ + x3 = _mm256_gf2p8affineinv_epi64_epi8(x3, x4, 3); + x3 = _mm256_mask_gf2p8affineinv_epi64_epi8(x3, m32, x4, x3, 3); + x3 = _mm256_maskz_gf2p8affineinv_epi64_epi8(m32, x3, x4, 3); + x5 = _mm_gf2p8affineinv_epi64_epi8(x5, x6, 3); + x5 = _mm_mask_gf2p8affineinv_epi64_epi8(x5, m16, x6, x5, 3); + x5 = _mm_maskz_gf2p8affineinv_epi64_epi8(m16, x5, x6, 3); +} diff --git a/gcc/testsuite/gcc.target/i386/gfni-3.c b/gcc/testsuite/gcc.target/i386/gfni-3.c new file mode 100644 index 0000000..de5f80b --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/gfni-3.c @@ -0,0 +1,17 @@ +/* { dg-do compile } */ +/* { dg-options "-mgfni -mavx -O2" } */ +/* { dg-final { scan-assembler-times "vgf2p8affineinvqb\[ \\t\]+\[^\{\n\]*\\\$3\[^\n\r]*%ymm\[0-9\]+\[^\n\r]*%ymm\[0-9\]+\[^\n\r]*%ymm\[0-9\]+(?:\n|\[ \\t\]+#)" 1 } } */ +/* { dg-final { scan-assembler-times "vgf2p8affineinvqb\[ \\t\]+\[^\{\n\]*\\\$3\[^\n\r]*%xmm\[0-9\]+\[^\n\r]*%xmm\[0-9\]+\[^\n\r]*%xmm\[0-9\]+(?:\n|\[ \\t\]+#)" 1 } } */ + +#include + +int *p; +volatile __m256i x3, x4; +volatile __m128i x5, x6; + +void extern +avx512vl_test (void) +{ + x3 = _mm256_gf2p8affineinv_epi64_epi8(x3, x4, 3); + x5 = _mm_gf2p8affineinv_epi64_epi8(x5, x6, 3); +} diff --git a/gcc/testsuite/gcc.target/i386/gfni-4.c b/gcc/testsuite/gcc.target/i386/gfni-4.c new file mode 100644 index 0000000..1532716 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/gfni-4.c @@ -0,0 +1,14 @@ +/* { dg-do compile } */ +/* { dg-options "-mgfni -O2" } */ +/* { dg-final { scan-assembler-times "gf2p8affineinvqb\[ \\t\]+\[^\{\n\]*\\\$3\[^\n\r]*%xmm\[0-9\]+\[^\n\r]*%xmm\[0-9\]+(?:\n|\[ \\t\]+#)" 1 } } */ + +#include + +int *p; +volatile __m128i x5, x6; + +void extern +avx512vl_test (void) +{ + x5 = _mm_gf2p8affineinv_epi64_epi8(x5, x6, 3); +} diff --git a/gcc/testsuite/gcc.target/i386/i386.exp b/gcc/testsuite/gcc.target/i386/i386.exp index eae2531..b2bdbfd 100644 --- a/gcc/testsuite/gcc.target/i386/i386.exp +++ b/gcc/testsuite/gcc.target/i386/i386.exp @@ -421,6 +421,21 @@ proc check_effective_target_avx512vpopcntdq { } { } "-mavx512vpopcntdq" ] } +# Return 1 if gfni instructions can be compiled. +proc check_effective_target_gfni { } { + return [check_no_compiler_messages gfni object { + typedef char __v16qi __attribute__ ((__vector_size__ (16))); + + __v16qi + _mm_gf2p8affineinv_epi64_epi8 (__v16qi __A, __v16qi __B, const int __C) + { + return (__v16qi) __builtin_ia32_vgf2p8affineinvqb_v16qi ((__v16qi) __A, + (__v16qi) __B, + 0); + } + } "-mgfni" ] +} + # If a testcase doesn't have special options, use these. global DEFAULT_CFLAGS if ![info exists DEFAULT_CFLAGS] then { diff --git a/gcc/testsuite/gcc.target/i386/sse-13.c b/gcc/testsuite/gcc.target/i386/sse-13.c index c5c43b1..3378c5d 100644 --- a/gcc/testsuite/gcc.target/i386/sse-13.c +++ b/gcc/testsuite/gcc.target/i386/sse-13.c @@ -620,4 +620,12 @@ #define __builtin_ia32_extracti64x2_256_mask(A, E, C, D) __builtin_ia32_extracti64x2_256_mask(A, 1, C, D) #define __builtin_ia32_extractf64x2_256_mask(A, E, C, D) __builtin_ia32_extractf64x2_256_mask(A, 1, C, D) +/* gfniintrin.h */ +#define __builtin_ia32_vgf2p8affineinvqb_v16qi(A, B, C) __builtin_ia32_vgf2p8affineinvqb_v16qi(A, B, 1) +#define __builtin_ia32_vgf2p8affineinvqb_v32qi(A, B, C) __builtin_ia32_vgf2p8affineinvqb_v32qi(A, B, 1) +#define __builtin_ia32_vgf2p8affineinvqb_v64qi(A, B, C) __builtin_ia32_vgf2p8affineinvqb_v64qi(A, B, 1) +#define __builtin_ia32_vgf2p8affineinvqb_v16qi_mask(A, B, C, D, E) __builtin_ia32_vgf2p8affineinvqb_v16qi_mask(A, B, 1, D, E) +#define __builtin_ia32_vgf2p8affineinvqb_v32qi_mask(A, B, C, D, E) __builtin_ia32_vgf2p8affineinvqb_v32qi_mask(A, B, 1, D, E) +#define __builtin_ia32_vgf2p8affineinvqb_v64qi_mask(A, B, C, D, E) __builtin_ia32_vgf2p8affineinvqb_v64qi_mask(A, B, 1, D, E) + #include diff --git a/gcc/testsuite/gcc.target/i386/sse-23.c b/gcc/testsuite/gcc.target/i386/sse-23.c index fc339a5..d2a301c 100644 --- a/gcc/testsuite/gcc.target/i386/sse-23.c +++ b/gcc/testsuite/gcc.target/i386/sse-23.c @@ -619,6 +619,14 @@ #define __builtin_ia32_extracti64x2_256_mask(A, E, C, D) __builtin_ia32_extracti64x2_256_mask(A, 1, C, D) #define __builtin_ia32_extractf64x2_256_mask(A, E, C, D) __builtin_ia32_extractf64x2_256_mask(A, 1, C, D) +/* gfniintrin.h */ +#define __builtin_ia32_vgf2p8affineinvqb_v16qi(A, B, C) __builtin_ia32_vgf2p8affineinvqb_v16qi(A, B, 1) +#define __builtin_ia32_vgf2p8affineinvqb_v32qi(A, B, C) __builtin_ia32_vgf2p8affineinvqb_v32qi(A, B, 1) +#define __builtin_ia32_vgf2p8affineinvqb_v64qi(A, B, C) __builtin_ia32_vgf2p8affineinvqb_v64qi(A, B, 1) +#define __builtin_ia32_vgf2p8affineinvqb_v16qi_mask(A, B, C, D, E) __builtin_ia32_vgf2p8affineinvqb_v16qi_mask(A, B, 1, D, E) +#define __builtin_ia32_vgf2p8affineinvqb_v32qi_mask(A, B, C, D, E) __builtin_ia32_vgf2p8affineinvqb_v32qi_mask(A, B, 1, D, E) +#define __builtin_ia32_vgf2p8affineinvqb_v64qi_mask(A, B, C, D, E) __builtin_ia32_vgf2p8affineinvqb_v64qi_mask(A, B, 1, D, E) + #pragma GCC target ("sse4a,3dnow,avx,avx2,fma4,xop,aes,pclmul,popcnt,abm,lzcnt,bmi,bmi2,tbm,lwp,fsgsbase,rdrnd,f16c,fma,rtm,rdseed,prfchw,adx,fxsr,xsaveopt,avx512f,avx512er,avx512cd,avx512pf,sha,prefetchwt1,xsavec,xsaves,clflushopt,avx512bw,avx512dq,avx512vl,avx512vbmi,avx512ifma,avx5124fmaps,avx5124vnniw,avx512vpopcntdq,clwb,mwaitx,clzero,pku,sgx,rdpid") #include -- 1.8.3.1