James Greenhalgh <james.greenha...@arm.com> writes: > On Wed, Aug 30, 2017 at 04:34:40PM +0100, Richard Sandiford wrote: >> Ping for a few AArch64 patches: >> >> [AArch64] Remove use of wider vector modes >> https://gcc.gnu.org/ml/gcc-patches/2017-08/msg01249.html >> >> [AArch64] Rename cmp_result iterator >> https://gcc.gnu.org/ml/gcc-patches/2017-08/msg01250.html >> >> [AArch64] Tighten address register subreg checks >> https://gcc.gnu.org/ml/gcc-patches/2017-08/msg01252.html > > I've reviewed these three, which all looked OK to me. > >> [AArch64] Tweak aarch64_classify_address interface >> https://gcc.gnu.org/ml/gcc-patches/2017-08/msg01251.html > > I've reviewed this one with a comment on avoiding the duplication > of the new enum values across the back end.
Thanks. >> [61/77] Use scalar_int_mode in the AArch64 port >> https://gcc.gnu.org/ml/gcc-patches/2017-07/msg00701.html >> >> [75/77] Use scalar_mode in the AArch64 port >> https://gcc.gnu.org/ml/gcc-patches/2017-07/msg00715.html > > Do you have a link to a short primer on what these changes do? I don't really > have any objections to them if that's the direction the rest of the compiler > is going in, but I also didn't really understand what was happening here. https://gcc.gnu.org/ml/gcc-patches/2017-07/msg00639.html describes the overall rationale for the changes. When SVE is added, AArch64 will be the one backend for which the size of a normal machine_mode is a variable rather than a constant. But scalar modes will continue to be constant-sized, so when dealing with them, it's better to use the new scalar mode classes where possible. Thanks, Richard
