Michael Collison wrote: > > The subtract instruction only reliably sets the N and Z flags. We convey this > information in > aarch64_seelct_cc_mode.
The SUBS and CMP set the N and Z flags identically - although they also set C and V, they are different if there is overflow. CC_NZmode is used after merging a compare with zero into an ALU instruction - generally N and Z are valid. This means that LT and GE condition codes must be translated into MI and PL (which happens in aarch64_get_condition_code_1). At a higher level like match.pd you could transform (x - y) < 0 into x < y if there is no signed overflow, but this isn't safe in RTL given source types are not available. Wilco > Trunk generates: > > lt: > sub w1, w0, w1 > mov w0, 10 > cmp w1, 0 > csel w0, w0, wzr, lt > ret > > With the patch we can eliminate the redundant subtract and now generate: > > lt: > cmp w0, w1 > mov w0, 10 > csel w0, w0, wzr, mi > ret
