Hello!
We have to use TARGET_SSE with TARGET_SSE_MATH in insn constraints.
2017-07-10 Uros Bizjak <ubiz...@gmail.com>
PR target/81375
* config/i386/i386.md (divsf3): Add TARGET_SSE to TARGET_SSE_MATH.
(rcpps): Ditto.
(*rsqrtsf2_sse): Ditto.
(rsqrtsf2): Ditto.
(div<mode>3): Macroize insn from divdf3 and divsf3
using MODEF mode iterator.
testsuite/ChangeLog:
2017-07-10 Uros Bizjak <ubiz...@gmail.com>
PR target/81375
* gcc.target/i386/pr81375.c: New test.
Bootstrapped and regression tested on x86_64-linux-gnu {,-m32}.
Committed to mainline, will be backported to release branches.
Uros.
Index: config/i386/i386.md
===================================================================
--- config/i386/i386.md (revision 250102)
+++ config/i386/i386.md (working copy)
@@ -5504,7 +5504,7 @@
(define_expand "floatunsdisf2"
[(use (match_operand:SF 0 "register_operand"))
(use (match_operand:DI 1 "nonimmediate_operand"))]
- "TARGET_64BIT && TARGET_SSE_MATH"
+ "TARGET_64BIT && TARGET_SSE && TARGET_SSE_MATH"
"x86_emit_floatuns (operands); DONE;")
(define_expand "floatunsdidf2"
@@ -7545,21 +7545,15 @@
(match_operand:XF 2 "register_operand")))]
"TARGET_80387")
-(define_expand "divdf3"
- [(set (match_operand:DF 0 "register_operand")
- (div:DF (match_operand:DF 1 "register_operand")
- (match_operand:DF 2 "nonimmediate_operand")))]
- "(TARGET_80387 && X87_ENABLE_ARITH (DFmode))
- || (TARGET_SSE2 && TARGET_SSE_MATH)")
-
-(define_expand "divsf3"
- [(set (match_operand:SF 0 "register_operand")
- (div:SF (match_operand:SF 1 "register_operand")
- (match_operand:SF 2 "nonimmediate_operand")))]
- "(TARGET_80387 && X87_ENABLE_ARITH (SFmode))
- || TARGET_SSE_MATH"
+(define_expand "div<mode>3"
+ [(set (match_operand:MODEF 0 "register_operand")
+ (div:MODEF (match_operand:MODEF 1 "register_operand")
+ (match_operand:MODEF 2 "nonimmediate_operand")))]
+ "(TARGET_80387 && X87_ENABLE_ARITH (<MODE>mode))
+ || (SSE_FLOAT_MODE_P (<MODE>mode) && TARGET_SSE_MATH)"
{
- if (TARGET_SSE_MATH
+ if (<MODE>mode == SFmode
+ && TARGET_SSE && TARGET_SSE_MATH
&& TARGET_RECIP_DIV
&& optimize_insn_for_speed_p ()
&& flag_finite_math_only && !flag_trapping_math
@@ -14050,7 +14044,7 @@
[(set (match_operand:SF 0 "register_operand" "=x")
(unspec:SF [(match_operand:SF 1 "nonimmediate_operand" "xm")]
UNSPEC_RCP))]
- "TARGET_SSE_MATH"
+ "TARGET_SSE && TARGET_SSE_MATH"
"%vrcpss\t{%1, %d0|%d0, %1}"
[(set_attr "type" "sse")
(set_attr "atom_sse_attr" "rcp")
@@ -14352,7 +14346,7 @@
[(set (match_operand:SF 0 "register_operand" "=x")
(unspec:SF [(match_operand:SF 1 "nonimmediate_operand" "xm")]
UNSPEC_RSQRT))]
- "TARGET_SSE_MATH"
+ "TARGET_SSE && TARGET_SSE_MATH"
"%vrsqrtss\t{%1, %d0|%d0, %1}"
[(set_attr "type" "sse")
(set_attr "atom_sse_attr" "rcp")
@@ -14364,7 +14358,7 @@
[(set (match_operand:SF 0 "register_operand")
(unspec:SF [(match_operand:SF 1 "nonimmediate_operand")]
UNSPEC_RSQRT))]
- "TARGET_SSE_MATH"
+ "TARGET_SSE && TARGET_SSE_MATH"
{
ix86_emit_swsqrtsf (operands[0], operands[1], SFmode, 1);
DONE;
@@ -14393,7 +14387,7 @@
|| (SSE_FLOAT_MODE_P (<MODE>mode) && TARGET_SSE_MATH)"
{
if (<MODE>mode == SFmode
- && TARGET_SSE_MATH
+ && TARGET_SSE && TARGET_SSE_MATH
&& TARGET_RECIP_SQRT
&& !optimize_function_for_size_p (cfun)
&& flag_finite_math_only && !flag_trapping_math
Index: testsuite/gcc.target/i386/pr81375.c
===================================================================
--- testsuite/gcc.target/i386/pr81375.c (nonexistent)
+++ testsuite/gcc.target/i386/pr81375.c (working copy)
@@ -0,0 +1,8 @@
+/* PR target/81375 */
+/* { dg-do compile { target ia32 } } */
+/* { dg-options "-mno-80387 -mno-sse -mfpmath=sse" } */
+
+float foo (float a, float b)
+{
+ return a / b;
+}
