Hi Mike,
On Thu, Jun 15, 2017 at 10:10:28PM -0400, Michael Meissner wrote:
> +(define_insn_and_split "vsx_set_v4sf_p9"
> + [(set (match_operand:V4SF 0 "gpc_reg_operand" "=wa")
> + (unspec:V4SF
> + [(match_operand:V4SF 1 "gpc_reg_operand" "0")
> + (match_operand:SF 2 "gpc_reg_operand" "ww")
> + (match_operand:QI 3 "const_0_to_3_operand" "n")]
> + UNSPEC_VSX_SET))
> + (clobber (match_scratch:SI 4 "=&wJwK"))]
> + "VECTOR_MEM_VSX_P (V4SFmode) && TARGET_P9_VECTOR"
> + "#"
> + "&& reload_completed"
I still don't think it is such a good idea to do all of this not until
after reload. It does of course allow you to play tricks with changing
register mode at will, like you do ;-)
All these unspecs are a similar problem: the RTL optimisers cannot do
much at all with it.
> + [(set_attr "type" "vecperm")
Is that a good type for this? I think the convert is more expensive
than the permutes? If so, that would be better (of course it only
matters for sched1, not super important).
> --- gcc/testsuite/gcc.target/powerpc/pr79799-1.c (nonexistent)
> +++ gcc/testsuite/gcc.target/powerpc/pr79799-1.c (working copy)
> @@ -0,0 +1,43 @@
> +/* { dg-do compile { target { powerpc64*-*-* && lp64 } } } */
Why not powerpc*-*-*?
> +/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } {
> "-mcpu=power9" } } */
> +/* { dg-require-effective-target powerpc_p9vector_ok } */
> +/* { dg-options "-mcpu=power9 -O2" } */
> +
> +#include <altivec.h>
> +
> +/* GCC 7.1 did not have a specialized method for inserting 32-bit floating
> point on
> + ISA 3.0 (power9) systems. */
That first line is a bit long.
The patch is okay for trunk and 7 with the testsuite nits taken care of.
Thanks,
Segher
