Hi!
On Fri, May 26, 2017 at 09:17:26AM -0700, Carl E. Love wrote:
> * config/rs6000/altivec.md: Add code generator for doublee, unsdoublee
> doubleov, unsdoubleov, doublehv, unsdoublehv, doublelv, unsdoublelv.
Please mention the full name of the define_*, i.e.
* config/rs6000/altivec.md (doublee<mode>2, unsdoubleev4si2,
doubleo<mode>2, [etc., write them all here]): New patterns.
> +;; Generate doublee
> +;; signed int/float to double convert words 0 and 2
> +(define_expand "doublee<mode>2"
> + [(set (match_operand:V2DF 0 "register_operand" "=v")
> + (match_operand:VSX_W 1 "register_operand" "v"))]
> + "TARGET_VSX"
Indent only two spaces please.
> +{
> + machine_mode op_mode = GET_MODE (operands[1]);
And esp. in the C function body.
> + if (VECTOR_ELT_ORDER_BIG)
> + {
> + /* Big endian word numbering for words in operand is 0 1 2 3.
> + Input words 0 and 2 are where they need to be. */
Dot space space.
> + conversion. */
> + rtx rtx_tmp;
> + rtx rtx_val = GEN_INT (1);
> +
> + rtx_tmp = gen_reg_rtx (op_mode);
> + emit_insn (gen_vsx_xxsldwi_<mode> (rtx_tmp,
> + operands[1], operands[1], rtx_val));
Indents should use a tab character instead of eight spaces.
Following parameters should be indented to the same level as the first:
emit_insn (gen_vsx_xxsldwi_<mode> (rtx_tmp, operands[1], operands[1],
rtx_val));
> + /* Want to convert the words 1 and 3.
> + Little endian word numbering for operand is 3 2 1 0.
> + Input words 3 and 1 are where they need to be.
> + */
The closing */ should not be on a line by itself.
> + { VSX_BUILTIN_VEC_DOUBLEE, VSX_BUILTIN_DOUBLEE_V4SI,
> + RS6000_BTI_V2DF, RS6000_BTI_V4SI, 0, 0 },
> + { VSX_BUILTIN_VEC_DOUBLEE, VSX_BUILTIN_UNS_DOUBLEE_V4SI,
> + RS6000_BTI_V2DF, RS6000_BTI_unsigned_V4SI, 0, 0 },
> + { VSX_BUILTIN_VEC_DOUBLEE, VSX_BUILTIN_DOUBLEE_V4SF,
> + RS6000_BTI_V2DF, RS6000_BTI_V4SF, 0, 0 },
> +
> + { VSX_BUILTIN_VEC_DOUBLEO, VSX_BUILTIN_DOUBLEO_V4SI,
> + RS6000_BTI_V2DF, RS6000_BTI_V4SI, 0, 0 },
> + { VSX_BUILTIN_VEC_DOUBLEO, VSX_BUILTIN_UNS_DOUBLEO_V4SI,
> + RS6000_BTI_V2DF, RS6000_BTI_unsigned_V4SI, 0, 0 },
> + { VSX_BUILTIN_VEC_DOUBLEO, VSX_BUILTIN_DOUBLEO_V4SF,
> + RS6000_BTI_V2DF, RS6000_BTI_V4SF, 0, 0 },
This second (and later) blocks have the indent of the second lines
different from how existing code does it (the first block is fine).
> --- /dev/null
> +++ b/gcc/testsuite/gcc.target/powerpc/builtins-3-runnable.c
> @@ -0,0 +1,83 @@
> +/* { dg-do run { target { powerpc*-*-linux* } } } */
> +/* { dg-require-effective-target vsx_hw } */
> +/* { dg-options "-O2 -mvsx" } */
Does this test work on power7? Or even compile? That is the minimum
you are requiring here.
Segher
