Hi, Add support for early expansion of vector eqv built-ins.
Bootstraps currently running. OK for trunk? Thanks, -Will [gcc] 2017-05-26 Will Schmidt <will_schm...@vnet.ibm.com> * config/rs6000/rs6000.c (rs6000_gimple_fold_builtin): Add handling for early expansion of vec_eqv. [gcc/testsuite] 2017-05-26 Will Schmidt <will_schm...@vnet.ibm.com> * testsuite/gcc.target/powerpc/fold-vec-logical-eqv-char.c: New. * testsuite/gcc.target/powerpc/fold-vec-logical-eqv-float.c: New. * testsuite/gcc.target/powerpc/fold-vec-logical-eqv-floatdouble.c: New. * testsuite/gcc.target/powerpc/fold-vec-logical-eqv-int.c: New. * testsuite/gcc.target/powerpc/fold-vec-logical-eqv-longlong.c: New. * testsuite/gcc.target/powerpc/fold-vec-logical-eqv-short.c: New. diff --git a/gcc/config/rs6000/rs6000.c b/gcc/config/rs6000/rs6000.c index ce6cc1b..8adbc06 100644 --- a/gcc/config/rs6000/rs6000.c +++ b/gcc/config/rs6000/rs6000.c @@ -17388,6 +17388,26 @@ rs6000_gimple_fold_builtin (gimple_stmt_iterator *gsi) gsi_replace (gsi, g, true); return true; } + /* Flavors of vec_eqv. */ + case P8V_BUILTIN_EQV_V16QI: + case P8V_BUILTIN_EQV_V8HI: + case P8V_BUILTIN_EQV_V4SI: + case P8V_BUILTIN_EQV_V4SF: + case P8V_BUILTIN_EQV_V2DF: + case P8V_BUILTIN_EQV_V2DI: + { + arg0 = gimple_call_arg (stmt, 0); + arg1 = gimple_call_arg (stmt, 1); + lhs = gimple_call_lhs (stmt); + tree temp = create_tmp_reg_or_ssa_name (TREE_TYPE (arg1)); + gimple *g = gimple_build_assign (temp, BIT_XOR_EXPR, arg0, arg1); + gimple_set_location (g, gimple_location (stmt)); + gsi_insert_before(gsi, g, GSI_SAME_STMT); + g = gimple_build_assign (lhs, BIT_NOT_EXPR, temp); + gimple_set_location (g, gimple_location (stmt)); + gsi_replace (gsi, g, true); + return true; + } default: break; } diff --git a/gcc/testsuite/gcc.target/powerpc/fold-vec-logical-eqv-char.c b/gcc/testsuite/gcc.target/powerpc/fold-vec-logical-eqv-char.c new file mode 100644 index 0000000..6810848 --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/fold-vec-logical-eqv-char.c @@ -0,0 +1,28 @@ +/* Verify that overloaded built-ins for vec_eqv with char + inputs produce the right results. */ + +/* { dg-do compile } */ +/* { dg-require-effective-target powerpc_p8vector_ok } */ +/* { dg-options "-mpower8-vector -O2" } */ + +#include <altivec.h> + +vector bool char +test1 (vector bool char x, vector bool char y) +{ + return vec_eqv (x, y); +} + +vector signed char +test3 (vector signed char x, vector signed char y) +{ + return vec_eqv (x, y); +} + +vector unsigned char +test6 (vector unsigned char x, vector unsigned char y) +{ + return vec_eqv (x, y); +} + +/* { dg-final { scan-assembler-times "xxleqv" 3 } } */ diff --git a/gcc/testsuite/gcc.target/powerpc/fold-vec-logical-eqv-float.c b/gcc/testsuite/gcc.target/powerpc/fold-vec-logical-eqv-float.c new file mode 100644 index 0000000..d206cfe --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/fold-vec-logical-eqv-float.c @@ -0,0 +1,16 @@ +/* Verify that overloaded built-ins for vec_eqv with float + inputs produce the right results. */ + +/* { dg-do compile } */ +/* { dg-require-effective-target powerpc_p8vector_ok } */ +/* { dg-options "-mpower8-vector -O2" } */ + +#include <altivec.h> + +vector float +test1 (vector float x, vector float y) +{ + return vec_eqv (x, y); +} + +/* { dg-final { scan-assembler-times "xxleqv" 1 } } */ diff --git a/gcc/testsuite/gcc.target/powerpc/fold-vec-logical-eqv-floatdouble.c b/gcc/testsuite/gcc.target/powerpc/fold-vec-logical-eqv-floatdouble.c new file mode 100644 index 0000000..56b7cac --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/fold-vec-logical-eqv-floatdouble.c @@ -0,0 +1,22 @@ +/* Verify that overloaded built-ins for vec_eqv with float and + double inputs for VSX produce the right results. */ + +/* { dg-do compile } */ +/* { dg-require-effective-target powerpc_p8vector_ok } */ +/* { dg-options "-mpower8-vector -O2" } */ + +#include <altivec.h> + +vector float +test1 (vector float x, vector float y) +{ + return vec_eqv (x, y); +} + +vector double +test2 (vector double x, vector double y) +{ + return vec_eqv (x, y); +} + +/* { dg-final { scan-assembler-times "xxleqv" 2 } } */ diff --git a/gcc/testsuite/gcc.target/powerpc/fold-vec-logical-eqv-int.c b/gcc/testsuite/gcc.target/powerpc/fold-vec-logical-eqv-int.c new file mode 100644 index 0000000..f5d292e --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/fold-vec-logical-eqv-int.c @@ -0,0 +1,28 @@ +/* Verify that overloaded built-ins for vec_eqv with int + inputs produce the right results. */ + +/* { dg-do compile } */ +/* { dg-require-effective-target powerpc_p8vector_ok } */ +/* { dg-options "-mpower8-vector -O2" } */ + +#include <altivec.h> + +vector bool int +test1 (vector bool int x, vector bool int y) +{ + return vec_eqv (x, y); +} + +vector signed int +test3 (vector signed int x, vector signed int y) +{ + return vec_eqv (x, y); +} + +vector unsigned int +test6 (vector unsigned int x, vector unsigned int y) +{ + return vec_eqv (x, y); +} + +/* { dg-final { scan-assembler-times "xxleqv" 3 } } */ diff --git a/gcc/testsuite/gcc.target/powerpc/fold-vec-logical-eqv-longlong.c b/gcc/testsuite/gcc.target/powerpc/fold-vec-logical-eqv-longlong.c new file mode 100644 index 0000000..342b2bd --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/fold-vec-logical-eqv-longlong.c @@ -0,0 +1,28 @@ +/* Verify that overloaded built-ins for vec_eqv with long long + inputs produce the right results. */ + +/* { dg-do compile } */ +/* { dg-require-effective-target powerpc_p8vector_ok } */ +/* { dg-options "-mpower8-vector -O2" } */ + +#include <altivec.h> + +vector bool long long +test1 (vector bool long long x, vector bool long long y) +{ + return vec_eqv (x, y); +} + +vector signed long long +test3 (vector signed long long x, vector signed long long y) +{ + return vec_eqv (x, y); +} + +vector unsigned long long +test6 (vector unsigned long long x, vector unsigned long long y) +{ + return vec_eqv (x, y); +} + +/* { dg-final { scan-assembler-times "xxleqv" 3 } } */ diff --git a/gcc/testsuite/gcc.target/powerpc/fold-vec-logical-eqv-short.c b/gcc/testsuite/gcc.target/powerpc/fold-vec-logical-eqv-short.c new file mode 100644 index 0000000..79ca8aa --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/fold-vec-logical-eqv-short.c @@ -0,0 +1,28 @@ +/* Verify that overloaded built-ins for vec_eqv with short + inputs produce the right results. */ + +/* { dg-do compile } */ +/* { dg-require-effective-target powerpc_p8vector_ok } */ +/* { dg-options "-mpower8-vector -O2" } */ + +#include <altivec.h> + +vector bool short +test1 (vector bool short x, vector bool short y) +{ + return vec_eqv (x, y); +} + +vector signed short +test3 (vector signed short x, vector signed short y) +{ + return vec_eqv (x, y); +} + +vector unsigned short +test6 (vector unsigned short x, vector unsigned short y) +{ + return vec_eqv (x, y); +} + +/* { dg-final { scan-assembler-times "xxleqv" 3 } } */