Hi Naveen,
> https://gcc.gnu.org/ml/gcc-patches/2017-03/msg01368.html
This looks good to me - I have just one comment:
--- a/gcc/config/aarch64/aarch64.c
+++ b/gcc/config/aarch64/aarch64.c
@@ -13972,6 +13972,15 @@ aarch_macro_fusion_pair_p (rtx_insn *prev, rtx_insn
*curr)
{
enum attr_type prev_type = get_attr_type (prev);
+ unsigned int condreg1, condreg2;
+ rtx cc_reg_1;
+ aarch64_fixed_condition_code_regs (&condreg1, &condreg2);
+ cc_reg_1 = gen_rtx_REG (CCmode, condreg1);
+ if (!reg_referenced_p (cc_reg_1, PATTERN (curr))
+ || !prev
+ || !modified_in_p (cc_reg_1, prev))
+ return false;
+
The return false seems incorrect - it means a core can either have
FUSE_CMP_BRANCH or
FUSE_ALU_BRANCH but not both.
The way aarch_macro_fusion_pair_p works is to return true if fusion is possible
but fallthrough
if not so other, less likely, fusion candidates can still be tried.
Wilco
