Hi,
Gerald, thanks for fixing my "excellent" English :)
Here is updated patch:
Index: htdocs/gcc-4.7/changes.html
===================================================================
RCS file: /cvs/gcc/wwwdocs/htdocs/gcc-4.7/changes.html,v
retrieving revision 1.28
diff -p -r1.28 changes.html
*** htdocs/gcc-4.7/changes.html 12 Sep 2011 07:46:05 -0000 1.28
--- htdocs/gcc-4.7/changes.html 27 Sep 2011 13:03:09 -0000
*************** struct F: E { }; // error: deriving from
*** 270,275 ****
--- 270,291 ----
<h3>IA-32/x86-64</h3>
<ul>
+ <li>Support for Intel AVX2 intrinsics, built-in functions and
code generation is
+ available via <code>-mavx2</code>.</li>
+ <li>Support for Intel BMI2 intrinsics, built-in functions and
code generation is
+ available via <code>-mbmi2</code>.</li>
+ <li>Implementation and automatic generation of
<code>__builtin_clz*</code>
+ using the <code>lzcnt</code> instruction is available via
<code>-mlzcnt</code>.</li>
+ <li>Support for Intel FMA3 intrinsics and code generation is available via
+ <code>-mfma</code>.</li>
+ <li>A new <code>-mfsgsbase</code> command-line option is
available that makes GCC
+ generate new segment register read/write instructions through
dedicated built-ins.</li>
+ <li>Support for new Intel <code>rdrnd</code> instruction is
available via <code>-mrdrnd</code>.</li>
+ <li>Two additional AVX vector conversion instructions are
available via <code>-mf16c</code>.</li>
+ <li>Support for new Intel processor codename IvyBridge with
RDRND, FSGSBASE and F16C
+ is available through <code>-march=core-avx-i</code>.
+ <li>Support for the new Intel processor codename Haswell with
AVX2, FMA, BMI,
+ BMI2, LZCNT is available through <code>-march=core-avx2</code>.
<li>...</li>
</ul>
So, if you are ok, let's wait a couple of days for maintainers inputs.
Thanks, K
