Jakub Jelinek wrote: > No. Some constants sometimes even 7 instructions (e.g. sparc64; not talking > in particular about 1ULL << 63 constant), or have one instruction > that is more expensive than normal small constant load. Compare say x86_64 > movl/movq vs. movabsq, I think the latter has 3 times longer latency on many > CPUs. So no, I think it isn't an unconditional win.
We're specifically only talking about the constants (1L << 63), (1 << 31) and (1 << 15). On all targets these need at most 2 simple instructions. That makes it an unconditional win. Wilco
