Both the fails in 80123 are a situation where vsx_splat_<mode> for V2DI
generates rtl for a mtvsrdd but constraint wr doesn't prevent
allocation of r0 for the input. So new constraint wA combines the
attributes of wr and b -- it is BASE_REGS if 64-bit and NO_REGS
otherwise.
Currently doing bootstrap/regtest on 64-bit LE and BE, and also BE 32-
bit. OK for trunk if everything passes?
2017-03-21 Aaron Sawdey <acsaw...@linux.vnet.ibm.com>
PR target/80123
* doc/md.texi (Constraints): Document wA constraint.
* config/rs6000/constraints.md (wA): New.
* config/rs6000/rs6000.c (rs6000_debug_reg_global): Add wA reg_class.
(rs6000_init_hard_regno_mode_ok): Init wA constraint.
* config/rs6000/rs6000.h (RS6000_CONSTRAINT_wA): New.
* config/rs6000/vsx.md (vsx_splat_<mode>): Use wA constraint.
--
Aaron Sawdey, Ph.D. acsaw...@linux.vnet.ibm.com
050-2/C113 (507) 253-7520 home: 507/263-0782
IBM Linux Technology Center - PPC ToolchainIndex: gcc/config/rs6000/constraints.md
===================================================================
--- gcc/config/rs6000/constraints.md (revision 246295)
+++ gcc/config/rs6000/constraints.md (working copy)
@@ -133,6 +133,9 @@
(define_register_constraint "wz" "rs6000_constraints[RS6000_CONSTRAINT_wz]"
"Floating point register if the LFIWZX instruction is enabled or NO_REGS.")
+(define_register_constraint "wA" "rs6000_constraints[RS6000_CONSTRAINT_wA]"
+ "BASE_REGS if 64-bit instructions are enabled or NO_REGS.")
+
;; wB needs ISA 2.07 VUPKHSW
(define_constraint "wB"
"Signed 5-bit constant integer that can be loaded into an altivec register."
Index: gcc/config/rs6000/rs6000.c
===================================================================
--- gcc/config/rs6000/rs6000.c (revision 246295)
+++ gcc/config/rs6000/rs6000.c (working copy)
@@ -2468,6 +2468,7 @@
"wx reg_class = %s\n"
"wy reg_class = %s\n"
"wz reg_class = %s\n"
+ "wA reg_class = %s\n"
"wH reg_class = %s\n"
"wI reg_class = %s\n"
"wJ reg_class = %s\n"
@@ -2500,6 +2501,7 @@
reg_class_names[rs6000_constraints[RS6000_CONSTRAINT_wx]],
reg_class_names[rs6000_constraints[RS6000_CONSTRAINT_wy]],
reg_class_names[rs6000_constraints[RS6000_CONSTRAINT_wz]],
+ reg_class_names[rs6000_constraints[RS6000_CONSTRAINT_wA]],
reg_class_names[rs6000_constraints[RS6000_CONSTRAINT_wH]],
reg_class_names[rs6000_constraints[RS6000_CONSTRAINT_wI]],
reg_class_names[rs6000_constraints[RS6000_CONSTRAINT_wJ]],
@@ -3210,7 +3212,10 @@
}
if (TARGET_POWERPC64)
- rs6000_constraints[RS6000_CONSTRAINT_wr] = GENERAL_REGS;
+ {
+ rs6000_constraints[RS6000_CONSTRAINT_wr] = GENERAL_REGS;
+ rs6000_constraints[RS6000_CONSTRAINT_wA] = BASE_REGS;
+ }
if (TARGET_P8_VECTOR && TARGET_UPPER_REGS_SF) /* SFmode */
{
Index: gcc/config/rs6000/rs6000.h
===================================================================
--- gcc/config/rs6000/rs6000.h (revision 246295)
+++ gcc/config/rs6000/rs6000.h (working copy)
@@ -1612,6 +1612,7 @@
RS6000_CONSTRAINT_wx, /* FPR register for STFIWX */
RS6000_CONSTRAINT_wy, /* VSX register for SF */
RS6000_CONSTRAINT_wz, /* FPR register for LFIWZX */
+ RS6000_CONSTRAINT_wA, /* BASE_REGS if 64-bit. */
RS6000_CONSTRAINT_wH, /* Altivec register for 32-bit integers. */
RS6000_CONSTRAINT_wI, /* VSX register for 32-bit integers. */
RS6000_CONSTRAINT_wJ, /* VSX register for 8/16-bit integers. */
Index: gcc/config/rs6000/vsx.md
===================================================================
--- gcc/config/rs6000/vsx.md (revision 246295)
+++ gcc/config/rs6000/vsx.md (working copy)
@@ -3072,7 +3072,7 @@
"=<VSa>, <VSa>,we,<VS_64dm>")
(vec_duplicate:VSX_D
(match_operand:<VS_scalar> 1 "splat_input_operand"
- "<VS_64reg>,Z, b, wr")))]
+ "<VS_64reg>,Z, b, wA")))]
"VECTOR_MEM_VSX_P (<MODE>mode)"
"@
xxpermdi %x0,%x1,%x1,0
Index: gcc/doc/md.texi
===================================================================
--- gcc/doc/md.texi (revision 246295)
+++ gcc/doc/md.texi (working copy)
@@ -3122,6 +3122,9 @@
@item wz
Floating point register if the LFIWZX instruction is enabled or NO_REGS.
+@item wA
+Address base register if 64-bit instructions are enabled or NO_REGS.
+
@item wB
Signed 5-bit constant integer that can be loaded into an altivec register.
