On Wed, Mar 15, 2017 at 8:20 AM, Wilco Dijkstra <wilco.dijks...@arm.com> wrote:
> Hi,
>
> I think the patch isn't quite complete yet. You will also need changes in
> generic code. Currently sched_macro_fuse_insns() does:
>
> if (any_condjump_p (insn))
> {
> unsigned int condreg1, condreg2;
> rtx cc_reg_1;
> targetm.fixed_condition_code_regs (&condreg1, &condreg2);
> cc_reg_1 = gen_rtx_REG (CCmode, condreg1);
> prev = prev_nonnote_nondebug_insn (insn);
> if (!reg_referenced_p (cc_reg_1, PATTERN (insn))
> || !prev
> || !modified_in_p (cc_reg_1, prev))
> return;
> }
>
> Ie. it explicitly looks for a flag-setting ALU instruction whose condition is
> used by a conditional branch, so none of the cases in your patch can match.
>
> Note this code also excludes all CBZ type branches as fusion candidates,
> is that intended too?
It is not intended that way; I did not even notice it after the
previous changes to make the macro_fusion more generic. I wonder how
this code ever worked for the folks before we started to touch it :).
Naveen,
Basically the idea is to push the check for CC usage into the target
macros (macro_fusion_pair_p in i386.c and aarch64.c are the only usage
of compare/branch fusion) instead of keeping it in the general code.
Also in aarch64.c's macro fusion you need check that the branch
instruction uses the same register as the other instruction sets like
the other code in this area.
Thanks,
Andrew Pinski
>
> Wilco
