On Fri, Feb 03, 2017 at 09:11:38PM +0100, Jakub Jelinek wrote:
> On Fri, Feb 03, 2017 at 03:05:58PM -0500, Michael Meissner wrote:
> > > > --- gcc/testsuite/gcc.target/powerpc/pr79354.c.jj 2017-02-03
> > > > 02:37:44.147938375 +0100
> > > > +++ gcc/testsuite/gcc.target/powerpc/pr79354.c 2017-02-03
> > > > 02:38:34.838303987 +0100
> > > > @@ -0,0 +1,23 @@
> > > > +/* PR target/79354 */
> > > > +/* { dg-do compile { target { powerpc64*-*-* && lp64 } } } */
> >
> > The code that moves SFmode vector registers to GPRs needs -m64 (the convert
> > from scalar format to vector format puts the converted SFmode value in the
> > upper 32-bits of the vector register, and then after the direct move, it
> > does a
> > 32-bit shift right in the GPR). Similarly, going from a GPR to a vector
> > register, we do a shift left 32-bits, direct move, and then convert from
> > vector
> > format to scalar format.
>
> The testcase is testing that the particular power9 instruction doesn't
> appear in -mcpu=power8 output. The test is valid source even for -m32 and
> should not contain the power9 instruction either.
> Without the rs6000.md change the test will only FAIL with -m64 indeed.
The function being patched (movsi_from_sf) will only be called when -m64 and
-mcpu=power9 or -mcpu=power8 are used. So, it doesn't harm anything to omit
the && lp64, but the fix being tested would only occur in 64-bit mode.
--
Michael Meissner, IBM
IBM, M/S 2506R, 550 King Street, Littleton, MA 01460-6245, USA
email: meiss...@linux.vnet.ibm.com, phone: +1 (978) 899-4797
