Hi Jakub,
On 27/01/17 16:30, Jakub Jelinek wrote:
Hi!
This patch attempts to document some new features (without warnings,
those are partially covered by Marek's patch, C++ FE (would be nice
to document -faligned-new, -fnew-inheriting-ctors, -fnew-ttp-matching,
-fstrong-eval-order and what from C++ is supported) and the BRIG FE).
Ok for wwwdocs?
<snip>
+
<h3 id="powerpc">PowerPC / PowerPC64 / RS6000</h3>
<ul>
<li>The PowerPC port now uses LRA by default.</li>
<li>GCC now diagnoses inline assembly that clobbers register r2.
This has always been invalid code, and is no longer quietly
tolerated.</li>
+ <li>Shrink-wrapping optimization can now separate portions of
+ prologues and epilogues to improve performance if some of the
+ work done traditionally by prologues and epilogues is not needed
+ on certain paths. This is controlled by the
+ <code>-fshrink-wrap-separate</code> option, enabled by default.</li>
</ul>
AArch64 also implements these hooks and so benefits from the optimisation as
well.
Perhaps move this to the general optimizer improvements section and mention
it's only
enabled for powerpc and aarch64 for the moment?
Kyrill
<!-- <h3 id="s390">S/390, System z, IBM z Systems</h3> -->
Jakub
