On Thu, Jan 26, 2017 at 10:14 AM, Thomas Schwinge
<tho...@codesourcery.com> wrote:
> Hi!
>
> On Fri, 20 Jan 2017 23:03:53 +0300, Andrew Senkevich
> <andrew.n.senkev...@gmail.com> wrote:
>> diff --git a/gcc/testsuite/gcc.target/i386/avx512f-ktestw-2.c
>> b/gcc/testsuite/gcc.target/i386/avx512f-ktestw-2.c
>> new file mode 100644
>> index 0000000..6602c7a
>> --- /dev/null
>> +++ b/gcc/testsuite/gcc.target/i386/avx512f-ktestw-2.c
>> @@ -0,0 +1,20 @@
>> +/* { dg-do run } */
>> +/* { dg-options "-O2 -mavx512f" } */
>> +/* { dg-require-effective-target avx512f } */
>> +
>> +#include "avx512f-check.h"
>> +
>> +void
>> +avx512f_test ()
>> +{
>> + volatile __mmask16 k1, k2;
>> + unsigned char r1, r2;
>> +
>> + __asm__( "kmovw %1, %0" : "=k" (k1) : "r" (0) );
>> + __asm__( "kmovw %1, %0" : "=k" (k2) : "r" (-1) );
>> +
>> + r1 = _ktest_mask16_u8(k1, k2, &r2);
>> +
>> + if (r1 != 1 || r2 != 0)
>> + abort ();
>> +}
>
> I see:
>
> {+FAIL: gcc.target/i386/avx512f-ktestw-2.c (test for excess errors)+}
> {+UNRESOLVED: gcc.target/i386/avx512f-ktestw-2.c compilation failed to
> produce executable+}
>
> ... because of:
>
> /tmp/ccjv3mX2.s: Assembler messages:
> /tmp/ccjv3mX2.s:26: Error: no such instruction: `ktestw %k1,%k0'
> compiler exited with status 1
The problem is with __builtin_ia32_ktesthi (and __builtin_ia32_kaddhi)
intrinsics. These should be enabled only with AVX512DQ, since
corresponding insns are available in AVX512DQ ISA extension.
Andrew, can you please adjust builtins, instruction patterns,
intrinsics and testcases? Also, can you please review if there are any
other inconsistencies w.r.t. ISA throughout mask intrinsics?
Uros.
