From: Kito Cheng <kito.ch...@gmail.com>
---
gcc/testsuite/g++.dg/cpp0x/constexpr-rom.C | 2 +-
gcc/testsuite/gcc.c-torture/execute/20101011-1.c | 3 +++
gcc/testsuite/gcc.dg/20020312-2.c | 2 ++
gcc/testsuite/gcc.dg/builtin-apply2.c | 1 +
gcc/testsuite/gcc.dg/ifcvt-4.c | 2 +-
gcc/testsuite/gcc.dg/loop-8.c | 2 +-
gcc/testsuite/gcc.dg/sibcall-9.c | 2 ++
gcc/testsuite/gcc.dg/stack-usage-1.c | 2 ++
gcc/testsuite/gcc.dg/torture/stackalign/builtin-apply-2.c | 2 +-
gcc/testsuite/gcc.dg/tree-ssa/20040204-1.c | 2 +-
gcc/testsuite/gcc.dg/tree-ssa/ssa-dom-cse-2.c | 2 +-
gcc/testsuite/gcc.dg/tree-ssa/ssa-fre-3.c | 2 +-
gcc/testsuite/lib/target-supports.exp | 1 +
13 files changed, 18 insertions(+), 7 deletions(-)
diff --git a/gcc/testsuite/g++.dg/cpp0x/constexpr-rom.C
b/gcc/testsuite/g++.dg/cpp0x/constexpr-rom.C
index 80a571a..2e0ef68 100644
--- a/gcc/testsuite/g++.dg/cpp0x/constexpr-rom.C
+++ b/gcc/testsuite/g++.dg/cpp0x/constexpr-rom.C
@@ -2,7 +2,7 @@
// { dg-do compile { target c++11 } }
// { dg-additional-options -G0 { target { { alpha*-*-* frv*-*-* ia64-*-*
lm32*-*-* m32r*-*-* microblaze*-*-* mips*-*-* nios2-*-* powerpc*-*-*
rs6000*-*-* } && { ! { *-*-darwin* *-*-aix* alpha*-*-*vms* } } } } }
// { dg-final { scan-assembler "\\.rdata" { target mips*-*-* } } }
-// { dg-final { scan-assembler "rodata" { target { { *-*-linux-gnu *-*-gnu*
*-*-elf } && { ! mips*-*-* } } } } }
+// { dg-final { scan-assembler "rodata" { target { { *-*-linux-gnu *-*-gnu*
*-*-elf } && { ! { mips*-*-* riscv*-*-* } } } } } }
struct Data
{
diff --git a/gcc/testsuite/gcc.c-torture/execute/20101011-1.c
b/gcc/testsuite/gcc.c-torture/execute/20101011-1.c
index 744763f..899a401 100644
--- a/gcc/testsuite/gcc.c-torture/execute/20101011-1.c
+++ b/gcc/testsuite/gcc.c-torture/execute/20101011-1.c
@@ -6,6 +6,9 @@
#elif defined (__powerpc__) || defined (__PPC__) || defined (__ppc__) ||
defined (__POWERPC__) || defined (__ppc)
/* On PPC division by zero does not trap. */
# define DO_TEST 0
+#elif defined (__riscv)
+ /* On RISC-V division by zero does not trap. */
+# define DO_TEST 0
#elif defined (__SPU__)
/* On SPU division by zero does not trap. */
# define DO_TEST 0
diff --git a/gcc/testsuite/gcc.dg/20020312-2.c
b/gcc/testsuite/gcc.dg/20020312-2.c
index 5fce50d..f5929e0 100644
--- a/gcc/testsuite/gcc.dg/20020312-2.c
+++ b/gcc/testsuite/gcc.dg/20020312-2.c
@@ -67,6 +67,8 @@ extern void abort (void);
# else
# define PIC_REG "30"
# endif
+#elif defined(__riscv)
+/* No pic register. */
#elif defined(__RX__)
/* No pic register. */
#elif defined(__s390__)
diff --git a/gcc/testsuite/gcc.dg/builtin-apply2.c
b/gcc/testsuite/gcc.dg/builtin-apply2.c
index b6cbe39..ad61d3b 100644
--- a/gcc/testsuite/gcc.dg/builtin-apply2.c
+++ b/gcc/testsuite/gcc.dg/builtin-apply2.c
@@ -1,6 +1,7 @@
/* { dg-do run } */
/* { dg-require-effective-target untyped_assembly } */
/* { dg-skip-if "Variadic funcs have all args on stack. Normal funcs have args
in registers." { "avr-*-* nds32*-*-*" } { "*" } { "" } } */
+/* { dg-skip-if "Variadic funcs use different argument passing from normal
funcs." { "riscv*-*-*" } { "*" } { "" } } */
/* { dg-skip-if "Variadic funcs use Base AAPCS. Normal funcs use VFP
variant." { arm*-*-* && arm_hf_eabi } { "*" } { "" } } */
/* PR target/12503 */
diff --git a/gcc/testsuite/gcc.dg/ifcvt-4.c b/gcc/testsuite/gcc.dg/ifcvt-4.c
index 0d1671c..466ad15 100644
--- a/gcc/testsuite/gcc.dg/ifcvt-4.c
+++ b/gcc/testsuite/gcc.dg/ifcvt-4.c
@@ -1,6 +1,6 @@
/* { dg-options "-fdump-rtl-ce1 -O2 --param max-rtl-if-conversion-insns=3
--param max-rtl-if-conversion-unpredictable-cost=100" } */
/* { dg-additional-options "-misel" { target { powerpc*-*-* } } } */
-/* { dg-skip-if "Multiple set if-conversion not guaranteed on all subtargets"
{ "arm*-*-* hppa*64*-*-* visium-*-*" } } */
+/* { dg-skip-if "Multiple set if-conversion not guaranteed on all subtargets"
{ "arm*-*-* hppa*64*-*-* visium-*-*" riscv*-*-* } } */
typedef int word __attribute__((mode(word)));
diff --git a/gcc/testsuite/gcc.dg/loop-8.c b/gcc/testsuite/gcc.dg/loop-8.c
index 8a4b209..fd4fa62 100644
--- a/gcc/testsuite/gcc.dg/loop-8.c
+++ b/gcc/testsuite/gcc.dg/loop-8.c
@@ -1,6 +1,6 @@
/* { dg-do compile } */
/* { dg-options "-O1 -fdump-rtl-loop2_invariant" } */
-/* { dg-skip-if "unexpected IV" { "hppa*-*-* mips*-*-* visium-*-*" } { "*" } {
"" } } */
+/* { dg-skip-if "unexpected IV" { "hppa*-*-* mips*-*-* visium-*-* riscv*-*-*"
} { "*" } { "" } } */
void
f (int *a, int *b)
diff --git a/gcc/testsuite/gcc.dg/sibcall-9.c b/gcc/testsuite/gcc.dg/sibcall-9.c
index 34e7053..8e30952 100644
--- a/gcc/testsuite/gcc.dg/sibcall-9.c
+++ b/gcc/testsuite/gcc.dg/sibcall-9.c
@@ -8,6 +8,8 @@
/* { dg-do run { xfail { { cris-*-* crisv32-*-* h8300-*-* hppa*64*-*-*
m32r-*-* mcore-*-* mn10300-*-* msp430*-*-* nds32*-*-* nvptx-*-* xstormy16-*-*
v850*-*-* vax-*-* xtensa*-*-* } || { arm*-*-* && { ! arm32 } } } } } */
/* -mlongcall disables sibcall patterns. */
/* { dg-skip-if "" { powerpc*-*-* } { "-mlongcall" } { "" } } */
+/* -msave-restore disables sibcall patterns. */
+/* { dg-skip-if "" { riscv*-*-* } { "-msave-restore" } { "" } } */
/* { dg-options "-O2 -foptimize-sibling-calls" } */
/* The option -foptimize-sibling-calls is the default, but serves as
diff --git a/gcc/testsuite/gcc.dg/stack-usage-1.c
b/gcc/testsuite/gcc.dg/stack-usage-1.c
index bdc5656..f10ba20 100644
--- a/gcc/testsuite/gcc.dg/stack-usage-1.c
+++ b/gcc/testsuite/gcc.dg/stack-usage-1.c
@@ -63,6 +63,8 @@
# else
# define SIZE 240
# endif
+#elif defined (__riscv)
+# define SIZE 240
#elif defined (__AVR__)
#if defined (__AVR_3_BYTE_PC__ )
# define SIZE 251 /* 256 - 2 bytes for Y - 3 bytes for return address */
diff --git a/gcc/testsuite/gcc.dg/torture/stackalign/builtin-apply-2.c
b/gcc/testsuite/gcc.dg/torture/stackalign/builtin-apply-2.c
index ffd865b..eb9d3a9 100644
--- a/gcc/testsuite/gcc.dg/torture/stackalign/builtin-apply-2.c
+++ b/gcc/testsuite/gcc.dg/torture/stackalign/builtin-apply-2.c
@@ -9,7 +9,7 @@
/* arm_hf_eabi: Variadic funcs use Base AAPCS. Normal funcs use VFP variant.
avr: Variadic funcs don't pass arguments in registers, while normal funcs
do. */
-/* { dg-skip-if "Variadic funcs use different argument passing from normal
funcs" { arm_hf_eabi || { avr-*-* } } "*" "" } */
+/* { dg-skip-if "Variadic funcs use different argument passing from normal
funcs" { arm_hf_eabi || { avr-*-* } || { riscv*-*-* } } "*" "" } */
/* { dg-skip-if "Variadic funcs have all args on stack. Normal funcs have args
in registers." { nds32*-*-* } "*" "" } */
/* { dg-require-effective-target untyped_assembly } */
diff --git a/gcc/testsuite/gcc.dg/tree-ssa/20040204-1.c
b/gcc/testsuite/gcc.dg/tree-ssa/20040204-1.c
index f7b5dfa..a1237cf 100644
--- a/gcc/testsuite/gcc.dg/tree-ssa/20040204-1.c
+++ b/gcc/testsuite/gcc.dg/tree-ssa/20040204-1.c
@@ -33,4 +33,4 @@ void test55 (int x, int y)
that the && should be emitted (based on BRANCH_COST). Fix this
by teaching dom to look through && and register all components
as true. */
-/* { dg-final { scan-tree-dump-times "link_error" 0 "optimized" { xfail { !
"alpha*-*-* arm*-*-* aarch64*-*-* powerpc*-*-* cris-*-* crisv32-*-* hppa*-*-*
i?86-*-* mmix-*-* mips*-*-* m68k*-*-* moxie-*-* nds32*-*-* s390*-*-* sh*-*-*
sparc*-*-* spu-*-* visium-*-* x86_64-*-*" } } } } */
+/* { dg-final { scan-tree-dump-times "link_error" 0 "optimized" { xfail { !
"alpha*-*-* arm*-*-* aarch64*-*-* powerpc*-*-* cris-*-* crisv32-*-* hppa*-*-*
i?86-*-* mmix-*-* mips*-*-* m68k*-*-* moxie-*-* nds32*-*-* s390*-*-* sh*-*-*
sparc*-*-* spu-*-* visium-*-* x86_64-*-* riscv*-*-*" } } } } */
diff --git a/gcc/testsuite/gcc.dg/tree-ssa/ssa-dom-cse-2.c
b/gcc/testsuite/gcc.dg/tree-ssa/ssa-dom-cse-2.c
index 1a4bfe6..665ac23 100644
--- a/gcc/testsuite/gcc.dg/tree-ssa/ssa-dom-cse-2.c
+++ b/gcc/testsuite/gcc.dg/tree-ssa/ssa-dom-cse-2.c
@@ -25,4 +25,4 @@ foo ()
but the loop reads only one element at a time, and DOM cannot resolve these.
The same happens on powerpc depending on the SIMD support available. */
-/* { dg-final { scan-tree-dump "return 28;" "optimized" { xfail { { alpha*-*-*
hppa*64*-*-* powerpc64*-*-* } || { sparc*-*-* && lp64 } } } } } */
+/* { dg-final { scan-tree-dump "return 28;" "optimized" { xfail { { alpha*-*-*
hppa*64*-*-* powerpc64*-*-* riscv*64*-*-* } || { sparc*-*-* && lp64 } } } } } */
diff --git a/gcc/testsuite/gcc.dg/tree-ssa/ssa-fre-3.c
b/gcc/testsuite/gcc.dg/tree-ssa/ssa-fre-3.c
index a287dad..0aecfed 100644
--- a/gcc/testsuite/gcc.dg/tree-ssa/ssa-fre-3.c
+++ b/gcc/testsuite/gcc.dg/tree-ssa/ssa-fre-3.c
@@ -5,7 +5,7 @@
When the condition is true, we distribute "(int) (a + b)" as
"(int) a + (int) b", otherwise we keep the original. */
-/* { dg-do compile { target { { ! mips64 } && { ! spu-*-* } } } } */
+/* { dg-do compile { target { { ! mips64 } && { { ! spu-*-* } && { !
riscv*64*-*-* } } } } } */
/* { dg-options "-O -fno-tree-forwprop -fno-tree-ccp -fwrapv
-fdump-tree-fre1-details" } */
/* From PR14844. */
diff --git a/gcc/testsuite/lib/target-supports.exp
b/gcc/testsuite/lib/target-supports.exp
index b88d13c..b22956b 100644
--- a/gcc/testsuite/lib/target-supports.exp
+++ b/gcc/testsuite/lib/target-supports.exp
@@ -7962,6 +7962,7 @@ proc check_effective_target_logical_op_short_circuit {} {
|| [istarget s390*-*-*]
|| [istarget powerpc*-*-*]
|| [istarget nios2*-*-*]
+ || [istarget riscv*-*-*]
|| [istarget visium-*-*]
|| [check_effective_target_arm_cortex_m] } {
return 1
--
2.10.2
