[PATCH] MIPS: Fix generation of DIV.G and MOD.G for Loongson targets.

[Toma Tabacu]

Hi,

The expand_DIVMOD function, introduced in r241660, will pick the divmod<mode>4
(or the udivmod<mode>4) pattern when it checks for the presence of hardware
div/mod instructions, which results in the generation of the old DIV
instruction.

Unfortunately, this interferes with the generation of DIV.G and MOD.G
(the <u>div<mode>3 and <u>mod<mode>3 patterns) for Loongson targets, which
causes test failures.

This patch prevents the selection of divmod<mode>4 and udivmod<mode>4 when
targeting Loongson by adding !ISA_HAS_DIV3 to the match condition.
ISA_HAS_DIV3 checks for the presence of the 3-operand Loongson-specific DIV.G
and MOD.G instructions.

Tested with mips-mti-elf.

This solution might be excessive, however, as it effectively forbids the
generation of the old DIV instruction for Loongson targets, which actually do
support it.

Is this OK ?

Regards,
Toma

gcc/ChangeLog:

        * config/mips/mips.md (divmod<mode>4): Add check for !ISA_HAS_DIV3.
        (udivmod<mode>4): Likewise.

diff --git a/gcc/config/mips/mips.md b/gcc/config/mips/mips.md
index 076cde6..f2fedcc 100644
--- a/gcc/config/mips/mips.md
+++ b/gcc/config/mips/mips.md
@@ -2851,7 +2851,7 @@
       (set (match_operand:GPR 3 "register_operand")
           (mod:GPR (match_dup 1)
                    (match_dup 2)))])]
-  "ISA_HAS_<D>DIV && !TARGET_FIX_VR4120"
+  "ISA_HAS_<D>DIV && !TARGET_FIX_VR4120 && !ISA_HAS_DIV3"
 {
   if (TARGET_MIPS16)
     {
@@ -2916,7 +2916,7 @@
       (set (match_operand:GPR 3 "register_operand")
           (umod:GPR (match_dup 1)
                     (match_dup 2)))])]
-  "ISA_HAS_<D>DIV && !TARGET_FIX_VR4120"
+  "ISA_HAS_<D>DIV && !TARGET_FIX_VR4120 && !ISA_HAS_DIV3"
 {
   if (TARGET_MIPS16)
     {