On Tue, Jan 3, 2017 at 4:43 PM, Michael Meissner
<meiss...@linux.vnet.ibm.com> wrote:
> In builting Spec 2006 with -mcpu=power9 with -O3, two of the benchmarks 
> (gamess
> and calculix) did not build due to an "insn does not match its constraints"
> error.
>
> (insn 2674 2673 2675 37 (parallel [
>             (set (reg:SI 0 0 [985])
>                 (vec_select:SI (reg:V4SI 32 0 [orig:378 vect__50.42 ] [378])
>                     (parallel [
>                             (const_int 1 [0x1])
>                         ])))
>             (clobber (reg:SI 31 31 [986]))
>         ]) "SPOOLES/MSMD/src/MSMD_init.c":113 1184 {vsx_extract_v4si_p9}
>      (expr_list:REG_UNUSED (reg:SI 31 31 [986])
>         (nil)))
>
> This insn was formed by vsx_extract_v4si_store_p9 splitting the following insn
> after register allocation:
>
> (insn 376 374 378 32 (parallel [
>             (set (mem:SI (plus:DI (reg:DI 7 7 [orig:394 ivtmp.316 ] [394])
>                         (const_int 112 [0x70])) [3 MEM[base: _399, offset: 
> 112B]+0 S4 A32])
>                 (vec_select:SI (reg:V4SI 32 0 [orig:355 vect__50.286 ] [355])
>                     (parallel [
>                             (const_int 2 [0x2])
>                         ])))
>             (clobber (reg:SI 9 9 [675]))
>             (clobber (reg:SI 10 10 [676]))
>         ]) "SPOOLES/MSMD/src/MSMD_init.c":113 1191 
> {*vsx_extract_v4si_store_p9}
>      (nil))
>
> It split it to:
>
> (insn 968 381 969 32 (parallel [
>             (set (reg:SI 44 12 [671])
>                 (vec_select:SI (reg:V4SI 32 0 [orig:355 vect__50.286 ] [355])
>                     (parallel [
>                             (const_int 0 [0])
>                         ])))
>             (clobber (scratch:SI))
>         ]) "SPOOLES/MSMD/src/MSMD_init.c":113 1185 {vsx_extract_v4si_p9}
>      (nil))
>
> Unfortunately, when it is splitting a word extract to be deposited into a GPR
> register, it needs to use a traditional Altivec register.
>
> The following patch fixes this:
>
> [gcc]
> 2017-01-03  Michael Meissner  <meiss...@linux.vnet.ibm.com>
>
>         PR target/78953
>         * config/rs6000/vsx.md (vsx_extract_<mode>_store_p9): If we are
>         extracting SImode to a GPR register so that we can generate a
>         store, limit the vector to be in a traditional Altivec register
>         for the vextuwrx instruction.
>
> [gcc/testsuite]
> 2017-01-03  Michael Meissner  <meiss...@linux.vnet.ibm.com>
>
>         PR target/78953
>         * gcc.target/powerpc/pr78953.c: New test.
>
> I did the usual bootstrap and make check with no regression on a little 
> endinan
> power8 system.  I also compiled the two Spec 2006 benchmarks that failed and
> they now build.  Is this ok for the trunk?  It does not need to be applied to
> GCC 6.x since the word extract optimization is new to GCC 7.

Okay.

Thanks, David

Reply via email to