On Fri, Dec 30, 2016 at 3:54 PM, Michael Meissner <meiss...@linux.vnet.ibm.com> wrote: > The signbit-3.c test explicitly tests for the value coming from memory, a > vector register, or a GPR. Unfortunately, the code did not handle splitting > up > the registers when the value was in a GPR. > > These patches add teh GPR support. While I was editing the code, I also did > some cleanup. > > I removed the Fsignbit mode attribute, since the only two modes used both use > the same attribute. This is a relic of the original code generation that also > provided optimized signbit support for DFmode/SFmode. Since the DFmode/SFmode > got dropped (GCC 6 was in stage 3, and we needed to get signbit working for > __float128 -- it already worked for DFmode/SFmode, but the code generation > could be improved). > > I also noticed that use of signbit tended to generate sign or zero extension. > Since the function only returns 0/1, I added combiner insns to eliminate the > extra zero/sign extend. > > I have tested this on both big endian and little endian power8 systems. The > bootstrap and make check had no regressions. Is this ok to put into the > trunk? > > The same error appears on GCC 6 as well. Assuming the patch applys cleanly > and > fixes the problem, can I install it on the GCC 6 branch as well after a burn > in > period? > > 2016-12-30 Michael Meissner <meiss...@linux.vnet.ibm.com> > > PR target/78900 > * config/rs6000/rs6000.c (rs6000_split_signbit): Change some > assertions. Add support for doing the signbit if the IEEE 128-bit > floating point value is in a GPR. > * config/rs6000/rs6000.md (Fsignbit): Delete. > (signbit<mode>2_dm): Delete using <Fsignbit> and just use "wa". > Update the length attribute if the value is in a GPR. > (signbit<mode>2_dm_<su>ext): Add combiner pattern to eliminate > the sign or zero extension instruction, since the value is always > 0/1. > (signbit<mode>2_dm2): Delete using <Fsignbit>.
This patch is okay for trunk and okay for GCC 6 branch after a week or two of no problems. Thanks, David
