2016-11-25 18:34 GMT+03:00 Georg-Johann Lay <a...@gjlay.de>: > Mentioned PR is about composing 16-bit values out of 8-bit values which due > to integer promotions likes to work on 16-bit values. > > The patch adds 3 combiner patterns to catch such situations and then split > after reload. Some more splitting is performed after reload for: > > and, ior, xor of reg-reg operations, > > HImode reg = 0 > > and 3- and 4-byte registers moves (and 2-byte moved if !MOVW). > > This gived better code for almost all test cases, yet some test cases could > still be improved. > > I also tried pre-reload splits, but the generated SUBREGs seem to disturb > register allocation, hence I used post-reload splits. > > There is also PR60145 which has a test case where a 4-byte value is composed > out of 4 bytes, but the patterns to catch that are going to be insane... so > for now, such 4-byte cases will still result in bloated code. > > Patch tested against trunk without regressions. > > Ok for trunk?
Ok. Please apply. > > Johann > > > PR 41076 > * config/avr/avr.md SPLIT34): New mode iterator. > (bitop): New code iterator. > (*iorhi3.ashift8-*). New insn-and-split patterns. > (*movhi): Post-reload split reg = 0. > (*movhi) [!MOVW]: Post-reload split reg = reg. > (*mov<mode>) [SI,SF,PSI,SQ,USQ,SA,USA]: Post-reload split reg = reg. > (andhi3, andpsi3, andsi3): Post-reload split reg-reg operations. > (iorhi3, iorpsi3, iorsi3): Same. > (xorhi3, xorpsi3, xorsi3): Same. > * config/avr/avr.c (avr_rtx_costs_1) [IOR && HImode]: Adjust rtx > costs to *iorhi3.ashift8-* patterns. >
