As per the subject. Tested by making sure that there were no new
warnings building arm-linux-gnueabi, and that there were no changes
in the assembly output for the C and C++ testsuite. OK to install?
Richard
gcc/
* config/arm/arm.md: Use match_test rather than eq/ne symbol_ref
throughout file.
* config/arm/neon.md: Likewise.
* config/arm/vfp.md: Likewise.
* config/arm/thumb2.md: Likewise.
* config/arm/cortex-m4.md: Likewise.
Index: gcc/config/arm/arm.md
===================================================================
--- gcc/config/arm/arm.md 2011-09-12 20:21:45.000000000 +0100
+++ gcc/config/arm/arm.md 2011-09-13 18:38:08.000000000 +0100
@@ -211,31 +211,31 @@ (define_attr "arch_enabled" "no,yes"
(const_string "yes")
(and (eq_attr "arch" "a")
- (ne (symbol_ref "TARGET_ARM") (const_int 0)))
+ (match_test "TARGET_ARM"))
(const_string "yes")
(and (eq_attr "arch" "t")
- (ne (symbol_ref "TARGET_THUMB") (const_int 0)))
+ (match_test "TARGET_THUMB"))
(const_string "yes")
(and (eq_attr "arch" "t1")
- (ne (symbol_ref "TARGET_THUMB1") (const_int 0)))
+ (match_test "TARGET_THUMB1"))
(const_string "yes")
(and (eq_attr "arch" "t2")
- (ne (symbol_ref "TARGET_THUMB2") (const_int 0)))
+ (match_test "TARGET_THUMB2"))
(const_string "yes")
(and (eq_attr "arch" "32")
- (ne (symbol_ref "TARGET_32BIT") (const_int 0)))
+ (match_test "TARGET_32BIT"))
(const_string "yes")
(and (eq_attr "arch" "v6")
- (ne (symbol_ref "(TARGET_32BIT && arm_arch6)") (const_int 0)))
+ (match_test "TARGET_32BIT && arm_arch6"))
(const_string "yes")
(and (eq_attr "arch" "nov6")
- (ne (symbol_ref "(TARGET_32BIT && !arm_arch6)") (const_int 0)))
+ (match_test "TARGET_32BIT && !arm_arch6"))
(const_string "yes")
(and (eq_attr "arch" "onlya8")
@@ -7413,7 +7413,7 @@ (define_insn "*arm_cond_branch"
(set_attr "type" "branch")
(set (attr "length")
(if_then_else
- (and (ne (symbol_ref "TARGET_THUMB2") (const_int 0))
+ (and (match_test "TARGET_THUMB2")
(and (ge (minus (match_dup 0) (pc)) (const_int -250))
(le (minus (match_dup 0) (pc)) (const_int 256))))
(const_int 2)
@@ -7439,7 +7439,7 @@ (define_insn "*arm_cond_branch_reversed"
(set_attr "type" "branch")
(set (attr "length")
(if_then_else
- (and (ne (symbol_ref "TARGET_THUMB2") (const_int 0))
+ (and (match_test "TARGET_THUMB2")
(and (ge (minus (match_dup 0) (pc)) (const_int -250))
(le (minus (match_dup 0) (pc)) (const_int 256))))
(const_int 2)
@@ -7898,7 +7898,7 @@ (define_insn "*arm_jump"
[(set_attr "predicable" "yes")
(set (attr "length")
(if_then_else
- (and (ne (symbol_ref "TARGET_THUMB2") (const_int 0))
+ (and (match_test "TARGET_THUMB2")
(and (ge (minus (match_dup 0) (pc)) (const_int -2044))
(le (minus (match_dup 0) (pc)) (const_int 2048))))
(const_int 2)
Index: gcc/config/arm/neon.md
===================================================================
--- gcc/config/arm/neon.md 2011-09-05 20:35:40.000000000 +0100
+++ gcc/config/arm/neon.md 2011-09-13 18:38:08.000000000 +0100
@@ -576,8 +576,8 @@ (define_insn "*add<mode>3_neon"
"TARGET_NEON && (!<Is_float_mode> || flag_unsafe_math_optimizations)"
"vadd.<V_if_elem>\t%<V_reg>0, %<V_reg>1, %<V_reg>2"
[(set (attr "neon_type")
- (if_then_else (ne (symbol_ref "<Is_float_mode>") (const_int 0))
- (if_then_else (ne (symbol_ref "<Is_d_reg>") (const_int 0))
+ (if_then_else (match_test "<Is_float_mode>")
+ (if_then_else (match_test "<Is_d_reg>")
(const_string "neon_fp_vadd_ddd_vabs_dd")
(const_string "neon_fp_vadd_qqq_vabs_qq"))
(const_string "neon_int_1")))]
@@ -612,8 +612,8 @@ (define_insn "*sub<mode>3_neon"
"TARGET_NEON && (!<Is_float_mode> || flag_unsafe_math_optimizations)"
"vsub.<V_if_elem>\t%<V_reg>0, %<V_reg>1, %<V_reg>2"
[(set (attr "neon_type")
- (if_then_else (ne (symbol_ref "<Is_float_mode>") (const_int 0))
- (if_then_else (ne (symbol_ref "<Is_d_reg>") (const_int 0))
+ (if_then_else (match_test "<Is_float_mode>")
+ (if_then_else (match_test "<Is_d_reg>")
(const_string "neon_fp_vadd_ddd_vabs_dd")
(const_string "neon_fp_vadd_qqq_vabs_qq"))
(const_string "neon_int_2")))]
@@ -649,16 +649,16 @@ (define_insn "*mul<mode>3_neon"
"TARGET_NEON && (!<Is_float_mode> || flag_unsafe_math_optimizations)"
"vmul.<V_if_elem>\t%<V_reg>0, %<V_reg>1, %<V_reg>2"
[(set (attr "neon_type")
- (if_then_else (ne (symbol_ref "<Is_float_mode>") (const_int 0))
- (if_then_else (ne (symbol_ref "<Is_d_reg>") (const_int 0))
+ (if_then_else (match_test "<Is_float_mode>")
+ (if_then_else (match_test "<Is_d_reg>")
(const_string "neon_fp_vadd_ddd_vabs_dd")
(const_string "neon_fp_vadd_qqq_vabs_qq"))
- (if_then_else (ne (symbol_ref "<Is_d_reg>") (const_int 0))
+ (if_then_else (match_test "<Is_d_reg>")
(if_then_else
- (ne (symbol_ref "<Scalar_mul_8_16>")
(const_int 0))
+ (match_test "<Scalar_mul_8_16>")
(const_string
"neon_mul_ddd_8_16_qdd_16_8_long_32_16_long")
(const_string
"neon_mul_qqq_8_16_32_ddd_32"))
- (if_then_else (ne (symbol_ref
"<Scalar_mul_8_16>") (const_int 0))
+ (if_then_else (match_test
"<Scalar_mul_8_16>")
(const_string
"neon_mul_qqq_8_16_32_ddd_32")
(const_string
"neon_mul_qqq_8_16_32_ddd_32")))))]
)
@@ -671,16 +671,16 @@ (define_insn "mul<mode>3add<mode>_neon"
"TARGET_NEON && (!<Is_float_mode> || flag_unsafe_math_optimizations)"
"vmla.<V_if_elem>\t%<V_reg>0, %<V_reg>2, %<V_reg>3"
[(set (attr "neon_type")
- (if_then_else (ne (symbol_ref "<Is_float_mode>") (const_int 0))
- (if_then_else (ne (symbol_ref "<Is_d_reg>") (const_int 0))
+ (if_then_else (match_test "<Is_float_mode>")
+ (if_then_else (match_test "<Is_d_reg>")
(const_string "neon_fp_vmla_ddd")
(const_string "neon_fp_vmla_qqq"))
- (if_then_else (ne (symbol_ref "<Is_d_reg>") (const_int 0))
+ (if_then_else (match_test "<Is_d_reg>")
(if_then_else
- (ne (symbol_ref "<Scalar_mul_8_16>")
(const_int 0))
+ (match_test "<Scalar_mul_8_16>")
(const_string
"neon_mla_ddd_8_16_qdd_16_8_long_32_16_long")
(const_string
"neon_mla_ddd_32_qqd_16_ddd_32_scalar_qdd_64_32_long_scalar_qdd_64_32_long"))
- (if_then_else (ne (symbol_ref
"<Scalar_mul_8_16>") (const_int 0))
+ (if_then_else (match_test
"<Scalar_mul_8_16>")
(const_string "neon_mla_qqq_8_16")
(const_string
"neon_mla_qqq_32_qqd_32_scalar")))))]
)
@@ -693,16 +693,16 @@ (define_insn "mul<mode>3neg<mode>add<mod
"TARGET_NEON && (!<Is_float_mode> || flag_unsafe_math_optimizations)"
"vmls.<V_if_elem>\t%<V_reg>0, %<V_reg>2, %<V_reg>3"
[(set (attr "neon_type")
- (if_then_else (ne (symbol_ref "<Is_float_mode>") (const_int 0))
- (if_then_else (ne (symbol_ref "<Is_d_reg>") (const_int 0))
+ (if_then_else (match_test "<Is_float_mode>")
+ (if_then_else (match_test "<Is_d_reg>")
(const_string "neon_fp_vmla_ddd")
(const_string "neon_fp_vmla_qqq"))
- (if_then_else (ne (symbol_ref "<Is_d_reg>") (const_int 0))
+ (if_then_else (match_test "<Is_d_reg>")
(if_then_else
- (ne (symbol_ref "<Scalar_mul_8_16>")
(const_int 0))
+ (match_test "<Scalar_mul_8_16>")
(const_string
"neon_mla_ddd_8_16_qdd_16_8_long_32_16_long")
(const_string
"neon_mla_ddd_32_qqd_16_ddd_32_scalar_qdd_64_32_long_scalar_qdd_64_32_long"))
- (if_then_else (ne (symbol_ref
"<Scalar_mul_8_16>") (const_int 0))
+ (if_then_else (match_test
"<Scalar_mul_8_16>")
(const_string "neon_mla_qqq_8_16")
(const_string
"neon_mla_qqq_32_qqd_32_scalar")))))]
)
@@ -902,8 +902,8 @@ (define_insn "abs<mode>2"
"TARGET_NEON"
"vabs.<V_s_elem>\t%<V_reg>0, %<V_reg>1"
[(set (attr "neon_type")
- (if_then_else (ne (symbol_ref "<Is_float_mode>") (const_int 0))
- (if_then_else (ne (symbol_ref "<Is_d_reg>") (const_int 0))
+ (if_then_else (match_test "<Is_float_mode>")
+ (if_then_else (match_test "<Is_d_reg>")
(const_string "neon_fp_vadd_ddd_vabs_dd")
(const_string "neon_fp_vadd_qqq_vabs_qq"))
(const_string "neon_int_3")))]
@@ -915,8 +915,8 @@ (define_insn "neg<mode>2"
"TARGET_NEON"
"vneg.<V_s_elem>\t%<V_reg>0, %<V_reg>1"
[(set (attr "neon_type")
- (if_then_else (ne (symbol_ref "<Is_float_mode>") (const_int 0))
- (if_then_else (ne (symbol_ref "<Is_d_reg>") (const_int 0))
+ (if_then_else (match_test "<Is_float_mode>")
+ (if_then_else (match_test "<Is_d_reg>")
(const_string "neon_fp_vadd_ddd_vabs_dd")
(const_string "neon_fp_vadd_qqq_vabs_qq"))
(const_string "neon_int_3")))]
@@ -947,7 +947,7 @@ (define_insn "*smin<mode>3_neon"
"TARGET_NEON"
"vmin.<V_s_elem>\t%<V_reg>0, %<V_reg>1, %<V_reg>2"
[(set (attr "neon_type")
- (if_then_else (ne (symbol_ref "<Is_float_mode>") (const_int 0))
+ (if_then_else (match_test "<Is_float_mode>")
(const_string "neon_fp_vadd_ddd_vabs_dd")
(const_string "neon_int_5")))]
)
@@ -959,7 +959,7 @@ (define_insn "*smax<mode>3_neon"
"TARGET_NEON"
"vmax.<V_s_elem>\t%<V_reg>0, %<V_reg>1, %<V_reg>2"
[(set (attr "neon_type")
- (if_then_else (ne (symbol_ref "<Is_float_mode>") (const_int 0))
+ (if_then_else (match_test "<Is_float_mode>")
(const_string "neon_fp_vadd_ddd_vabs_dd")
(const_string "neon_int_5")))]
)
@@ -985,7 +985,7 @@ (define_insn "vashl<mode>3"
}
}
[(set (attr "neon_type")
- (if_then_else (ne (symbol_ref "<Is_d_reg>") (const_int 0))
+ (if_then_else (match_test "<Is_d_reg>")
(const_string "neon_vshl_ddd")
(const_string "neon_shift_3")))]
)
@@ -1001,7 +1001,7 @@ (define_insn "vashr<mode>3_imm"
false);
}
[(set (attr "neon_type")
- (if_then_else (ne (symbol_ref "<Is_d_reg>") (const_int 0))
+ (if_then_else (match_test "<Is_d_reg>")
(const_string "neon_vshl_ddd")
(const_string "neon_shift_3")))]
)
@@ -1017,7 +1017,7 @@ (define_insn "vlshr<mode>3_imm"
false);
}
[(set (attr "neon_type")
- (if_then_else (ne (symbol_ref "<Is_d_reg>") (const_int 0))
+ (if_then_else (match_test "<Is_d_reg>")
(const_string "neon_vshl_ddd")
(const_string "neon_shift_3")))]
)
@@ -1035,7 +1035,7 @@ (define_insn "ashl<mode>3_signed"
"TARGET_NEON"
"vshl.<V_s_elem>\t%<V_reg>0, %<V_reg>1, %<V_reg>2"
[(set (attr "neon_type")
- (if_then_else (ne (symbol_ref "<Is_d_reg>") (const_int 0))
+ (if_then_else (match_test "<Is_d_reg>")
(const_string "neon_vshl_ddd")
(const_string "neon_shift_3")))]
)
@@ -1051,7 +1051,7 @@ (define_insn "ashl<mode>3_unsigned"
"TARGET_NEON"
"vshl.<V_u_elem>\t%<V_reg>0, %<V_reg>1, %<V_reg>2"
[(set (attr "neon_type")
- (if_then_else (ne (symbol_ref "<Is_d_reg>") (const_int 0))
+ (if_then_else (match_test "<Is_d_reg>")
(const_string "neon_vshl_ddd")
(const_string "neon_shift_3")))]
)
@@ -1491,8 +1491,8 @@ (define_insn "neon_vpadd_internal<mode>"
"vpadd.<V_if_elem>\t%P0, %P1, %P2"
;; Assume this schedules like vadd.
[(set (attr "neon_type")
- (if_then_else (ne (symbol_ref "<Is_float_mode>") (const_int 0))
- (if_then_else (ne (symbol_ref "<Is_d_reg>") (const_int 0))
+ (if_then_else (match_test "<Is_float_mode>")
+ (if_then_else (match_test "<Is_d_reg>")
(const_string "neon_fp_vadd_ddd_vabs_dd")
(const_string "neon_fp_vadd_qqq_vabs_qq"))
(const_string "neon_int_1")))]
@@ -1507,7 +1507,7 @@ (define_insn "neon_vpsmin<mode>"
"vpmin.<V_s_elem>\t%P0, %P1, %P2"
;; Assume this schedules like vmin.
[(set (attr "neon_type")
- (if_then_else (ne (symbol_ref "<Is_float_mode>") (const_int 0))
+ (if_then_else (match_test "<Is_float_mode>")
(const_string "neon_fp_vadd_ddd_vabs_dd")
(const_string "neon_int_5")))]
)
@@ -1521,7 +1521,7 @@ (define_insn "neon_vpsmax<mode>"
"vpmax.<V_s_elem>\t%P0, %P1, %P2"
;; Assume this schedules like vmax.
[(set (attr "neon_type")
- (if_then_else (ne (symbol_ref "<Is_float_mode>") (const_int 0))
+ (if_then_else (match_test "<Is_float_mode>")
(const_string "neon_fp_vadd_ddd_vabs_dd")
(const_string "neon_int_5")))]
)
@@ -1794,8 +1794,8 @@ (define_insn "neon_vadd<mode>_unspec"
"TARGET_NEON"
"vadd.<V_if_elem>\t%<V_reg>0, %<V_reg>1, %<V_reg>2"
[(set (attr "neon_type")
- (if_then_else (ne (symbol_ref "<Is_float_mode>") (const_int 0))
- (if_then_else (ne (symbol_ref "<Is_d_reg>") (const_int 0))
+ (if_then_else (match_test "<Is_float_mode>")
+ (if_then_else (match_test "<Is_d_reg>")
(const_string "neon_fp_vadd_ddd_vabs_dd")
(const_string "neon_fp_vadd_qqq_vabs_qq"))
(const_string "neon_int_1")))]
@@ -1873,16 +1873,16 @@ (define_insn "neon_vmul<mode>"
"TARGET_NEON"
"vmul.%F3%#<V_sz_elem>\t%<V_reg>0, %<V_reg>1, %<V_reg>2"
[(set (attr "neon_type")
- (if_then_else (ne (symbol_ref "<Is_float_mode>") (const_int 0))
- (if_then_else (ne (symbol_ref "<Is_d_reg>") (const_int 0))
+ (if_then_else (match_test "<Is_float_mode>")
+ (if_then_else (match_test "<Is_d_reg>")
(const_string "neon_fp_vadd_ddd_vabs_dd")
(const_string "neon_fp_vadd_qqq_vabs_qq"))
- (if_then_else (ne (symbol_ref "<Is_d_reg>") (const_int 0))
+ (if_then_else (match_test "<Is_d_reg>")
(if_then_else
- (ne (symbol_ref "<Scalar_mul_8_16>")
(const_int 0))
+ (match_test "<Scalar_mul_8_16>")
(const_string
"neon_mul_ddd_8_16_qdd_16_8_long_32_16_long")
(const_string
"neon_mul_qqq_8_16_32_ddd_32"))
- (if_then_else (ne (symbol_ref
"<Scalar_mul_8_16>") (const_int 0))
+ (if_then_else (match_test
"<Scalar_mul_8_16>")
(const_string
"neon_mul_qqq_8_16_32_ddd_32")
(const_string
"neon_mul_qqq_8_16_32_ddd_32")))))]
)
@@ -1915,16 +1915,16 @@ (define_insn "neon_vmla<mode>_unspec"
"TARGET_NEON"
"vmla.<V_if_elem>\t%<V_reg>0, %<V_reg>2, %<V_reg>3"
[(set (attr "neon_type")
- (if_then_else (ne (symbol_ref "<Is_float_mode>") (const_int 0))
- (if_then_else (ne (symbol_ref "<Is_d_reg>") (const_int 0))
+ (if_then_else (match_test "<Is_float_mode>")
+ (if_then_else (match_test "<Is_d_reg>")
(const_string "neon_fp_vmla_ddd")
(const_string "neon_fp_vmla_qqq"))
- (if_then_else (ne (symbol_ref "<Is_d_reg>") (const_int 0))
+ (if_then_else (match_test "<Is_d_reg>")
(if_then_else
- (ne (symbol_ref "<Scalar_mul_8_16>")
(const_int 0))
+ (match_test "<Scalar_mul_8_16>")
(const_string
"neon_mla_ddd_8_16_qdd_16_8_long_32_16_long")
(const_string
"neon_mla_ddd_32_qqd_16_ddd_32_scalar_qdd_64_32_long_scalar_qdd_64_32_long"))
- (if_then_else (ne (symbol_ref
"<Scalar_mul_8_16>") (const_int 0))
+ (if_then_else (match_test
"<Scalar_mul_8_16>")
(const_string "neon_mla_qqq_8_16")
(const_string
"neon_mla_qqq_32_qqd_32_scalar")))))]
)
@@ -1939,7 +1939,7 @@ (define_insn "neon_vmlal<mode>"
"TARGET_NEON"
"vmlal.%T4%#<V_sz_elem>\t%q0, %P2, %P3"
[(set (attr "neon_type")
- (if_then_else (ne (symbol_ref "<Scalar_mul_8_16>") (const_int 0))
+ (if_then_else (match_test "<Scalar_mul_8_16>")
(const_string "neon_mla_ddd_8_16_qdd_16_8_long_32_16_long")
(const_string
"neon_mla_ddd_32_qqd_16_ddd_32_scalar_qdd_64_32_long_scalar_qdd_64_32_long")))]
)
@@ -1972,17 +1972,17 @@ (define_insn "neon_vmls<mode>_unspec"
"TARGET_NEON"
"vmls.<V_if_elem>\t%<V_reg>0, %<V_reg>2, %<V_reg>3"
[(set (attr "neon_type")
- (if_then_else (ne (symbol_ref "<Is_float_mode>") (const_int 0))
- (if_then_else (ne (symbol_ref "<Is_d_reg>") (const_int 0))
+ (if_then_else (match_test "<Is_float_mode>")
+ (if_then_else (match_test "<Is_d_reg>")
(const_string "neon_fp_vmla_ddd")
(const_string "neon_fp_vmla_qqq"))
- (if_then_else (ne (symbol_ref "<Is_d_reg>") (const_int 0))
+ (if_then_else (match_test "<Is_d_reg>")
(if_then_else
- (ne (symbol_ref "<Scalar_mul_8_16>")
(const_int 0))
+ (match_test "<Scalar_mul_8_16>")
(const_string
"neon_mla_ddd_8_16_qdd_16_8_long_32_16_long")
(const_string
"neon_mla_ddd_32_qqd_16_ddd_32_scalar_qdd_64_32_long_scalar_qdd_64_32_long"))
(if_then_else
- (ne (symbol_ref "<Scalar_mul_8_16>")
(const_int 0))
+ (match_test "<Scalar_mul_8_16>")
(const_string "neon_mla_qqq_8_16")
(const_string
"neon_mla_qqq_32_qqd_32_scalar")))))]
)
@@ -1997,7 +1997,7 @@ (define_insn "neon_vmlsl<mode>"
"TARGET_NEON"
"vmlsl.%T4%#<V_sz_elem>\t%q0, %P2, %P3"
[(set (attr "neon_type")
- (if_then_else (ne (symbol_ref "<Scalar_mul_8_16>") (const_int 0))
+ (if_then_else (match_test "<Scalar_mul_8_16>")
(const_string "neon_mla_ddd_8_16_qdd_16_8_long_32_16_long")
(const_string
"neon_mla_ddd_32_qqd_16_ddd_32_scalar_qdd_64_32_long_scalar_qdd_64_32_long")))]
)
@@ -2011,11 +2011,11 @@ (define_insn "neon_vqdmulh<mode>"
"TARGET_NEON"
"vq%O3dmulh.<V_s_elem>\t%<V_reg>0, %<V_reg>1, %<V_reg>2"
[(set (attr "neon_type")
- (if_then_else (ne (symbol_ref "<Is_d_reg>") (const_int 0))
- (if_then_else (ne (symbol_ref "<Scalar_mul_8_16>") (const_int 0))
+ (if_then_else (match_test "<Is_d_reg>")
+ (if_then_else (match_test "<Scalar_mul_8_16>")
(const_string
"neon_mul_ddd_8_16_qdd_16_8_long_32_16_long")
(const_string "neon_mul_qqq_8_16_32_ddd_32"))
- (if_then_else (ne (symbol_ref "<Scalar_mul_8_16>") (const_int 0))
+ (if_then_else (match_test "<Scalar_mul_8_16>")
(const_string "neon_mul_qqq_8_16_32_ddd_32")
(const_string "neon_mul_qqq_8_16_32_ddd_32"))))]
)
@@ -2030,7 +2030,7 @@ (define_insn "neon_vqdmlal<mode>"
"TARGET_NEON"
"vqdmlal.<V_s_elem>\t%q0, %P2, %P3"
[(set (attr "neon_type")
- (if_then_else (ne (symbol_ref "<Scalar_mul_8_16>") (const_int 0))
+ (if_then_else (match_test "<Scalar_mul_8_16>")
(const_string "neon_mla_ddd_8_16_qdd_16_8_long_32_16_long")
(const_string
"neon_mla_ddd_32_qqd_16_ddd_32_scalar_qdd_64_32_long_scalar_qdd_64_32_long")))]
)
@@ -2045,7 +2045,7 @@ (define_insn "neon_vqdmlsl<mode>"
"TARGET_NEON"
"vqdmlsl.<V_s_elem>\t%q0, %P2, %P3"
[(set (attr "neon_type")
- (if_then_else (ne (symbol_ref "<Scalar_mul_8_16>") (const_int 0))
+ (if_then_else (match_test "<Scalar_mul_8_16>")
(const_string "neon_mla_ddd_8_16_qdd_16_8_long_32_16_long")
(const_string
"neon_mla_ddd_32_qqd_16_ddd_32_scalar_qdd_64_32_long_scalar_qdd_64_32_long")))]
)
@@ -2059,7 +2059,7 @@ (define_insn "neon_vmull<mode>"
"TARGET_NEON"
"vmull.%T3%#<V_sz_elem>\t%q0, %P1, %P2"
[(set (attr "neon_type")
- (if_then_else (ne (symbol_ref "<Scalar_mul_8_16>") (const_int 0))
+ (if_then_else (match_test "<Scalar_mul_8_16>")
(const_string "neon_mul_ddd_8_16_qdd_16_8_long_32_16_long")
(const_string
"neon_mul_qdd_64_32_long_qqd_16_ddd_32_scalar_64_32_long_scalar")))]
)
@@ -2073,7 +2073,7 @@ (define_insn "neon_vqdmull<mode>"
"TARGET_NEON"
"vqdmull.<V_s_elem>\t%q0, %P1, %P2"
[(set (attr "neon_type")
- (if_then_else (ne (symbol_ref "<Scalar_mul_8_16>") (const_int 0))
+ (if_then_else (match_test "<Scalar_mul_8_16>")
(const_string "neon_mul_ddd_8_16_qdd_16_8_long_32_16_long")
(const_string
"neon_mul_qdd_64_32_long_qqd_16_ddd_32_scalar_64_32_long_scalar")))]
)
@@ -2103,8 +2103,8 @@ (define_insn "neon_vsub<mode>_unspec"
"TARGET_NEON"
"vsub.<V_if_elem>\t%<V_reg>0, %<V_reg>1, %<V_reg>2"
[(set (attr "neon_type")
- (if_then_else (ne (symbol_ref "<Is_float_mode>") (const_int 0))
- (if_then_else (ne (symbol_ref "<Is_d_reg>") (const_int 0))
+ (if_then_else (match_test "<Is_float_mode>")
+ (if_then_else (match_test "<Is_d_reg>")
(const_string "neon_fp_vadd_ddd_vabs_dd")
(const_string "neon_fp_vadd_qqq_vabs_qq"))
(const_string "neon_int_2")))]
@@ -2177,8 +2177,8 @@ (define_insn "neon_vceq<mode>"
vceq.<V_if_elem>\t%<V_reg>0, %<V_reg>1, %<V_reg>2
vceq.<V_if_elem>\t%<V_reg>0, %<V_reg>1, #0"
[(set (attr "neon_type")
- (if_then_else (ne (symbol_ref "<Is_float_mode>") (const_int 0))
- (if_then_else (ne (symbol_ref "<Is_d_reg>") (const_int 0))
+ (if_then_else (match_test "<Is_float_mode>")
+ (if_then_else (match_test "<Is_d_reg>")
(const_string "neon_fp_vadd_ddd_vabs_dd")
(const_string "neon_fp_vadd_qqq_vabs_qq"))
(const_string "neon_int_5")))]
@@ -2196,8 +2196,8 @@ (define_insn "neon_vcge<mode>"
vcge.%T3%#<V_sz_elem>\t%<V_reg>0, %<V_reg>1, %<V_reg>2
vcge.%T3%#<V_sz_elem>\t%<V_reg>0, %<V_reg>1, #0"
[(set (attr "neon_type")
- (if_then_else (ne (symbol_ref "<Is_float_mode>") (const_int 0))
- (if_then_else (ne (symbol_ref "<Is_d_reg>") (const_int 0))
+ (if_then_else (match_test "<Is_float_mode>")
+ (if_then_else (match_test "<Is_d_reg>")
(const_string "neon_fp_vadd_ddd_vabs_dd")
(const_string "neon_fp_vadd_qqq_vabs_qq"))
(const_string "neon_int_5")))]
@@ -2215,8 +2215,8 @@ (define_insn "neon_vcgt<mode>"
vcgt.%T3%#<V_sz_elem>\t%<V_reg>0, %<V_reg>1, %<V_reg>2
vcgt.%T3%#<V_sz_elem>\t%<V_reg>0, %<V_reg>1, #0"
[(set (attr "neon_type")
- (if_then_else (ne (symbol_ref "<Is_float_mode>") (const_int 0))
- (if_then_else (ne (symbol_ref "<Is_d_reg>") (const_int 0))
+ (if_then_else (match_test "<Is_float_mode>")
+ (if_then_else (match_test "<Is_d_reg>")
(const_string "neon_fp_vadd_ddd_vabs_dd")
(const_string "neon_fp_vadd_qqq_vabs_qq"))
(const_string "neon_int_5")))]
@@ -2235,8 +2235,8 @@ (define_insn "neon_vcle<mode>"
"TARGET_NEON"
"vcle.%T3%#<V_sz_elem>\t%<V_reg>0, %<V_reg>1, #0"
[(set (attr "neon_type")
- (if_then_else (ne (symbol_ref "<Is_float_mode>") (const_int 0))
- (if_then_else (ne (symbol_ref "<Is_d_reg>") (const_int 0))
+ (if_then_else (match_test "<Is_float_mode>")
+ (if_then_else (match_test "<Is_d_reg>")
(const_string "neon_fp_vadd_ddd_vabs_dd")
(const_string "neon_fp_vadd_qqq_vabs_qq"))
(const_string "neon_int_5")))]
@@ -2252,8 +2252,8 @@ (define_insn "neon_vclt<mode>"
"TARGET_NEON"
"vclt.%T3%#<V_sz_elem>\t%<V_reg>0, %<V_reg>1, #0"
[(set (attr "neon_type")
- (if_then_else (ne (symbol_ref "<Is_float_mode>") (const_int 0))
- (if_then_else (ne (symbol_ref "<Is_d_reg>") (const_int 0))
+ (if_then_else (match_test "<Is_float_mode>")
+ (if_then_else (match_test "<Is_d_reg>")
(const_string "neon_fp_vadd_ddd_vabs_dd")
(const_string "neon_fp_vadd_qqq_vabs_qq"))
(const_string "neon_int_5")))]
@@ -2268,7 +2268,7 @@ (define_insn "neon_vcage<mode>"
"TARGET_NEON"
"vacge.<V_if_elem>\t%<V_reg>0, %<V_reg>1, %<V_reg>2"
[(set (attr "neon_type")
- (if_then_else (ne (symbol_ref "<Is_d_reg>") (const_int 0))
+ (if_then_else (match_test "<Is_d_reg>")
(const_string "neon_fp_vadd_ddd_vabs_dd")
(const_string "neon_fp_vadd_qqq_vabs_qq")))]
)
@@ -2282,7 +2282,7 @@ (define_insn "neon_vcagt<mode>"
"TARGET_NEON"
"vacgt.<V_if_elem>\t%<V_reg>0, %<V_reg>1, %<V_reg>2"
[(set (attr "neon_type")
- (if_then_else (ne (symbol_ref "<Is_d_reg>") (const_int 0))
+ (if_then_else (match_test "<Is_d_reg>")
(const_string "neon_fp_vadd_ddd_vabs_dd")
(const_string "neon_fp_vadd_qqq_vabs_qq")))]
)
@@ -2307,8 +2307,8 @@ (define_insn "neon_vabd<mode>"
"TARGET_NEON"
"vabd.%T3%#<V_sz_elem>\t%<V_reg>0, %<V_reg>1, %<V_reg>2"
[(set (attr "neon_type")
- (if_then_else (ne (symbol_ref "<Is_float_mode>") (const_int 0))
- (if_then_else (ne (symbol_ref "<Is_d_reg>") (const_int 0))
+ (if_then_else (match_test "<Is_float_mode>")
+ (if_then_else (match_test "<Is_d_reg>")
(const_string "neon_fp_vadd_ddd_vabs_dd")
(const_string "neon_fp_vadd_qqq_vabs_qq"))
(const_string "neon_int_5")))]
@@ -2335,7 +2335,7 @@ (define_insn "neon_vaba<mode>"
"TARGET_NEON"
"vaba.%T4%#<V_sz_elem>\t%<V_reg>0, %<V_reg>2, %<V_reg>3"
[(set (attr "neon_type")
- (if_then_else (ne (symbol_ref "<Is_d_reg>") (const_int 0))
+ (if_then_else (match_test "<Is_d_reg>")
(const_string "neon_vaba") (const_string "neon_vaba_qqq")))]
)
@@ -2360,8 +2360,8 @@ (define_insn "neon_vmax<mode>"
"TARGET_NEON"
"vmax.%T3%#<V_sz_elem>\t%<V_reg>0, %<V_reg>1, %<V_reg>2"
[(set (attr "neon_type")
- (if_then_else (ne (symbol_ref "<Is_float_mode>") (const_int 0))
- (if_then_else (ne (symbol_ref "<Is_d_reg>") (const_int 0))
+ (if_then_else (match_test "<Is_float_mode>")
+ (if_then_else (match_test "<Is_d_reg>")
(const_string "neon_fp_vadd_ddd_vabs_dd")
(const_string "neon_fp_vadd_qqq_vabs_qq"))
(const_string "neon_int_5")))]
@@ -2376,8 +2376,8 @@ (define_insn "neon_vmin<mode>"
"TARGET_NEON"
"vmin.%T3%#<V_sz_elem>\t%<V_reg>0, %<V_reg>1, %<V_reg>2"
[(set (attr "neon_type")
- (if_then_else (ne (symbol_ref "<Is_float_mode>") (const_int 0))
- (if_then_else (ne (symbol_ref "<Is_d_reg>") (const_int 0))
+ (if_then_else (match_test "<Is_float_mode>")
+ (if_then_else (match_test "<Is_d_reg>")
(const_string "neon_fp_vadd_ddd_vabs_dd")
(const_string "neon_fp_vadd_qqq_vabs_qq"))
(const_string "neon_int_5")))]
@@ -2428,7 +2428,7 @@ (define_insn "neon_vpmax<mode>"
"vpmax.%T3%#<V_sz_elem>\t%<V_reg>0, %<V_reg>1, %<V_reg>2"
;; Assume this schedules like vmax.
[(set (attr "neon_type")
- (if_then_else (ne (symbol_ref "<Is_float_mode>") (const_int 0))
+ (if_then_else (match_test "<Is_float_mode>")
(const_string "neon_fp_vadd_ddd_vabs_dd")
(const_string "neon_int_5")))]
)
@@ -2443,7 +2443,7 @@ (define_insn "neon_vpmin<mode>"
"vpmin.%T3%#<V_sz_elem>\t%<V_reg>0, %<V_reg>1, %<V_reg>2"
;; Assume this schedules like vmin.
[(set (attr "neon_type")
- (if_then_else (ne (symbol_ref "<Is_float_mode>") (const_int 0))
+ (if_then_else (match_test "<Is_float_mode>")
(const_string "neon_fp_vadd_ddd_vabs_dd")
(const_string "neon_int_5")))]
)
@@ -2457,7 +2457,7 @@ (define_insn "neon_vrecps<mode>"
"TARGET_NEON"
"vrecps.<V_if_elem>\t%<V_reg>0, %<V_reg>1, %<V_reg>2"
[(set (attr "neon_type")
- (if_then_else (ne (symbol_ref "<Is_d_reg>") (const_int 0))
+ (if_then_else (match_test "<Is_d_reg>")
(const_string "neon_fp_vrecps_vrsqrts_ddd")
(const_string "neon_fp_vrecps_vrsqrts_qqq")))]
)
@@ -2471,7 +2471,7 @@ (define_insn "neon_vrsqrts<mode>"
"TARGET_NEON"
"vrsqrts.<V_if_elem>\t%<V_reg>0, %<V_reg>1, %<V_reg>2"
[(set (attr "neon_type")
- (if_then_else (ne (symbol_ref "<Is_d_reg>") (const_int 0))
+ (if_then_else (match_test "<Is_d_reg>")
(const_string "neon_fp_vrecps_vrsqrts_ddd")
(const_string "neon_fp_vrecps_vrsqrts_qqq")))]
)
@@ -2570,7 +2570,7 @@ (define_insn "neon_vrecpe<mode>"
"TARGET_NEON"
"vrecpe.<V_u_elem>\t%<V_reg>0, %<V_reg>1"
[(set (attr "neon_type")
- (if_then_else (ne (symbol_ref "<Is_d_reg>") (const_int 0))
+ (if_then_else (match_test "<Is_d_reg>")
(const_string "neon_fp_vadd_ddd_vabs_dd")
(const_string "neon_fp_vadd_qqq_vabs_qq")))]
)
@@ -2583,7 +2583,7 @@ (define_insn "neon_vrsqrte<mode>"
"TARGET_NEON"
"vrsqrte.<V_u_elem>\t%<V_reg>0, %<V_reg>1"
[(set (attr "neon_type")
- (if_then_else (ne (symbol_ref "<Is_d_reg>") (const_int 0))
+ (if_then_else (match_test "<Is_d_reg>")
(const_string "neon_fp_vadd_ddd_vabs_dd")
(const_string "neon_fp_vadd_qqq_vabs_qq")))]
)
@@ -3155,7 +3155,7 @@ (define_insn "neon_vcvt<mode>"
"TARGET_NEON"
"vcvt.%T2%#32.f32\t%<V_reg>0, %<V_reg>1"
[(set (attr "neon_type")
- (if_then_else (ne (symbol_ref "<Is_d_reg>") (const_int 0))
+ (if_then_else (match_test "<Is_d_reg>")
(const_string "neon_fp_vadd_ddd_vabs_dd")
(const_string "neon_fp_vadd_qqq_vabs_qq")))]
)
@@ -3168,7 +3168,7 @@ (define_insn "neon_vcvt<mode>"
"TARGET_NEON"
"vcvt.f32.%T2%#32\t%<V_reg>0, %<V_reg>1"
[(set (attr "neon_type")
- (if_then_else (ne (symbol_ref "<Is_d_reg>") (const_int 0))
+ (if_then_else (match_test "<Is_d_reg>")
(const_string "neon_fp_vadd_ddd_vabs_dd")
(const_string "neon_fp_vadd_qqq_vabs_qq")))]
)
@@ -3185,7 +3185,7 @@ (define_insn "neon_vcvt_n<mode>"
return "vcvt.%T3%#32.f32\t%<V_reg>0, %<V_reg>1, %2";
}
[(set (attr "neon_type")
- (if_then_else (ne (symbol_ref "<Is_d_reg>") (const_int 0))
+ (if_then_else (match_test "<Is_d_reg>")
(const_string "neon_fp_vadd_ddd_vabs_dd")
(const_string "neon_fp_vadd_qqq_vabs_qq")))]
)
@@ -3202,7 +3202,7 @@ (define_insn "neon_vcvt_n<mode>"
return "vcvt.f32.%T3%#32\t%<V_reg>0, %<V_reg>1, %2";
}
[(set (attr "neon_type")
- (if_then_else (ne (symbol_ref "<Is_d_reg>") (const_int 0))
+ (if_then_else (match_test "<Is_d_reg>")
(const_string "neon_fp_vadd_ddd_vabs_dd")
(const_string "neon_fp_vadd_qqq_vabs_qq")))]
)
@@ -3261,9 +3261,9 @@ (define_insn "neon_vmul_lane<mode>"
return "vmul.<V_if_elem>\t%P0, %P1, %P2[%c3]";
}
[(set (attr "neon_type")
- (if_then_else (ne (symbol_ref "<Is_float_mode>") (const_int 0))
+ (if_then_else (match_test "<Is_float_mode>")
(const_string "neon_fp_vmul_ddd")
- (if_then_else (ne (symbol_ref "<Scalar_mul_8_16>")
(const_int 0))
+ (if_then_else (match_test "<Scalar_mul_8_16>")
(const_string
"neon_mul_ddd_16_scalar_32_16_long_scalar")
(const_string
"neon_mul_qdd_64_32_long_qqd_16_ddd_32_scalar_64_32_long_scalar"))))]
)
@@ -3282,9 +3282,9 @@ (define_insn "neon_vmul_lane<mode>"
return "vmul.<V_if_elem>\t%q0, %q1, %P2[%c3]";
}
[(set (attr "neon_type")
- (if_then_else (ne (symbol_ref "<Is_float_mode>") (const_int 0))
+ (if_then_else (match_test "<Is_float_mode>")
(const_string "neon_fp_vmul_qqd")
- (if_then_else (ne (symbol_ref "<Scalar_mul_8_16>")
(const_int 0))
+ (if_then_else (match_test "<Scalar_mul_8_16>")
(const_string
"neon_mul_qdd_64_32_long_qqd_16_ddd_32_scalar_64_32_long_scalar")
(const_string "neon_mul_qqd_32_scalar"))))]
)
@@ -3303,7 +3303,7 @@ (define_insn "neon_vmull_lane<mode>"
return "vmull.%T4%#<V_sz_elem>\t%q0, %P1, %P2[%c3]";
}
[(set (attr "neon_type")
- (if_then_else (ne (symbol_ref "<Scalar_mul_8_16>") (const_int 0))
+ (if_then_else (match_test "<Scalar_mul_8_16>")
(const_string "neon_mul_ddd_16_scalar_32_16_long_scalar")
(const_string
"neon_mul_qdd_64_32_long_qqd_16_ddd_32_scalar_64_32_long_scalar")))]
)
@@ -3322,7 +3322,7 @@ (define_insn "neon_vqdmull_lane<mode>"
return "vqdmull.<V_s_elem>\t%q0, %P1, %P2[%c3]";
}
[(set (attr "neon_type")
- (if_then_else (ne (symbol_ref "<Scalar_mul_8_16>") (const_int 0))
+ (if_then_else (match_test "<Scalar_mul_8_16>")
(const_string "neon_mul_ddd_16_scalar_32_16_long_scalar")
(const_string
"neon_mul_qdd_64_32_long_qqd_16_ddd_32_scalar_64_32_long_scalar")))]
)
@@ -3341,7 +3341,7 @@ (define_insn "neon_vqdmulh_lane<mode>"
return "vq%O4dmulh.%T4%#<V_sz_elem>\t%q0, %q1, %P2[%c3]";
}
[(set (attr "neon_type")
- (if_then_else (ne (symbol_ref "<Scalar_mul_8_16>") (const_int 0))
+ (if_then_else (match_test "<Scalar_mul_8_16>")
(const_string
"neon_mul_qdd_64_32_long_qqd_16_ddd_32_scalar_64_32_long_scalar")
(const_string "neon_mul_qqd_32_scalar")))]
)
@@ -3360,7 +3360,7 @@ (define_insn "neon_vqdmulh_lane<mode>"
return "vq%O4dmulh.%T4%#<V_sz_elem>\t%P0, %P1, %P2[%c3]";
}
[(set (attr "neon_type")
- (if_then_else (ne (symbol_ref "<Scalar_mul_8_16>") (const_int 0))
+ (if_then_else (match_test "<Scalar_mul_8_16>")
(const_string "neon_mul_ddd_16_scalar_32_16_long_scalar")
(const_string
"neon_mul_qdd_64_32_long_qqd_16_ddd_32_scalar_64_32_long_scalar")))]
)
@@ -3380,9 +3380,9 @@ (define_insn "neon_vmla_lane<mode>"
return "vmla.<V_if_elem>\t%P0, %P2, %P3[%c4]";
}
[(set (attr "neon_type")
- (if_then_else (ne (symbol_ref "<Is_float_mode>") (const_int 0))
+ (if_then_else (match_test "<Is_float_mode>")
(const_string "neon_fp_vmla_ddd_scalar")
- (if_then_else (ne (symbol_ref "<Scalar_mul_8_16>")
(const_int 0))
+ (if_then_else (match_test "<Scalar_mul_8_16>")
(const_string
"neon_mla_ddd_16_scalar_qdd_32_16_long_scalar")
(const_string
"neon_mla_ddd_32_qqd_16_ddd_32_scalar_qdd_64_32_long_scalar_qdd_64_32_long"))))]
)
@@ -3402,9 +3402,9 @@ (define_insn "neon_vmla_lane<mode>"
return "vmla.<V_if_elem>\t%q0, %q2, %P3[%c4]";
}
[(set (attr "neon_type")
- (if_then_else (ne (symbol_ref "<Is_float_mode>") (const_int 0))
+ (if_then_else (match_test "<Is_float_mode>")
(const_string "neon_fp_vmla_qqq_scalar")
- (if_then_else (ne (symbol_ref "<Scalar_mul_8_16>")
(const_int 0))
+ (if_then_else (match_test "<Scalar_mul_8_16>")
(const_string
"neon_mla_ddd_32_qqd_16_ddd_32_scalar_qdd_64_32_long_scalar_qdd_64_32_long")
(const_string
"neon_mla_qqq_32_qqd_32_scalar"))))]
)
@@ -3424,7 +3424,7 @@ (define_insn "neon_vmlal_lane<mode>"
return "vmlal.%T5%#<V_sz_elem>\t%q0, %P2, %P3[%c4]";
}
[(set (attr "neon_type")
- (if_then_else (ne (symbol_ref "<Scalar_mul_8_16>") (const_int 0))
+ (if_then_else (match_test "<Scalar_mul_8_16>")
(const_string
"neon_mla_ddd_16_scalar_qdd_32_16_long_scalar")
(const_string
"neon_mla_ddd_32_qqd_16_ddd_32_scalar_qdd_64_32_long_scalar_qdd_64_32_long")))]
)
@@ -3444,7 +3444,7 @@ (define_insn "neon_vqdmlal_lane<mode>"
return "vqdmlal.<V_s_elem>\t%q0, %P2, %P3[%c4]";
}
[(set (attr "neon_type")
- (if_then_else (ne (symbol_ref "<Scalar_mul_8_16>") (const_int 0))
+ (if_then_else (match_test "<Scalar_mul_8_16>")
(const_string
"neon_mla_ddd_16_scalar_qdd_32_16_long_scalar")
(const_string
"neon_mla_ddd_32_qqd_16_ddd_32_scalar_qdd_64_32_long_scalar_qdd_64_32_long")))]
)
@@ -3464,9 +3464,9 @@ (define_insn "neon_vmls_lane<mode>"
return "vmls.<V_if_elem>\t%P0, %P2, %P3[%c4]";
}
[(set (attr "neon_type")
- (if_then_else (ne (symbol_ref "<Is_float_mode>") (const_int 0))
+ (if_then_else (match_test "<Is_float_mode>")
(const_string "neon_fp_vmla_ddd_scalar")
- (if_then_else (ne (symbol_ref "<Scalar_mul_8_16>")
(const_int 0))
+ (if_then_else (match_test "<Scalar_mul_8_16>")
(const_string
"neon_mla_ddd_16_scalar_qdd_32_16_long_scalar")
(const_string
"neon_mla_ddd_32_qqd_16_ddd_32_scalar_qdd_64_32_long_scalar_qdd_64_32_long"))))]
)
@@ -3486,9 +3486,9 @@ (define_insn "neon_vmls_lane<mode>"
return "vmls.<V_if_elem>\t%q0, %q2, %P3[%c4]";
}
[(set (attr "neon_type")
- (if_then_else (ne (symbol_ref "<Is_float_mode>") (const_int 0))
+ (if_then_else (match_test "<Is_float_mode>")
(const_string "neon_fp_vmla_qqq_scalar")
- (if_then_else (ne (symbol_ref "<Scalar_mul_8_16>")
(const_int 0))
+ (if_then_else (match_test "<Scalar_mul_8_16>")
(const_string
"neon_mla_ddd_32_qqd_16_ddd_32_scalar_qdd_64_32_long_scalar_qdd_64_32_long")
(const_string
"neon_mla_qqq_32_qqd_32_scalar"))))]
)
@@ -3508,7 +3508,7 @@ (define_insn "neon_vmlsl_lane<mode>"
return "vmlsl.%T5%#<V_sz_elem>\t%q0, %P2, %P3[%c4]";
}
[(set (attr "neon_type")
- (if_then_else (ne (symbol_ref "<Scalar_mul_8_16>") (const_int 0))
+ (if_then_else (match_test "<Scalar_mul_8_16>")
(const_string
"neon_mla_ddd_16_scalar_qdd_32_16_long_scalar")
(const_string
"neon_mla_ddd_32_qqd_16_ddd_32_scalar_qdd_64_32_long_scalar_qdd_64_32_long")))]
)
@@ -3528,7 +3528,7 @@ (define_insn "neon_vqdmlsl_lane<mode>"
return "vqdmlsl.<V_s_elem>\t%q0, %P2, %P3[%c4]";
}
[(set (attr "neon_type")
- (if_then_else (ne (symbol_ref "<Scalar_mul_8_16>") (const_int 0))
+ (if_then_else (match_test "<Scalar_mul_8_16>")
(const_string
"neon_mla_ddd_16_scalar_qdd_32_16_long_scalar")
(const_string
"neon_mla_ddd_32_qqd_16_ddd_32_scalar_qdd_64_32_long_scalar_qdd_64_32_long")))]
)
@@ -3756,7 +3756,7 @@ (define_insn "neon_vext<mode>"
return "vext.<V_sz_elem>\t%<V_reg>0, %<V_reg>1, %<V_reg>2, %3";
}
[(set (attr "neon_type")
- (if_then_else (ne (symbol_ref "<Is_d_reg>") (const_int 0))
+ (if_then_else (match_test "<Is_d_reg>")
(const_string "neon_bp_simple")
(const_string "neon_bp_2cycle")))]
)
@@ -3834,7 +3834,7 @@ (define_insn "neon_vshl<mode>"
"TARGET_NEON"
"v%O3shl.%T3%#<V_sz_elem>\t%<V_reg>0, %<V_reg>1, %<V_reg>2"
[(set (attr "neon_type")
- (if_then_else (ne (symbol_ref "<Is_d_reg>") (const_int 0))
+ (if_then_else (match_test "<Is_d_reg>")
(const_string "neon_vshl_ddd")
(const_string "neon_shift_3")))]
)
@@ -3848,7 +3848,7 @@ (define_insn "neon_vqshl<mode>"
"TARGET_NEON"
"vq%O3shl.%T3%#<V_sz_elem>\t%<V_reg>0, %<V_reg>1, %<V_reg>2"
[(set (attr "neon_type")
- (if_then_else (ne (symbol_ref "<Is_d_reg>") (const_int 0))
+ (if_then_else (match_test "<Is_d_reg>")
(const_string "neon_shift_2")
(const_string "neon_vqshl_vrshl_vqrshl_qqq")))]
)
@@ -3993,7 +3993,7 @@ (define_insn "neon_vsri_n<mode>"
return "vsri.<V_sz_elem>\t%<V_reg>0, %<V_reg>2, %3";
}
[(set (attr "neon_type")
- (if_then_else (ne (symbol_ref "<Is_d_reg>") (const_int 0))
+ (if_then_else (match_test "<Is_d_reg>")
(const_string "neon_shift_1")
(const_string "neon_shift_3")))]
)
@@ -4010,7 +4010,7 @@ (define_insn "neon_vsli_n<mode>"
return "vsli.<V_sz_elem>\t%<V_reg>0, %<V_reg>2, %3";
}
[(set (attr "neon_type")
- (if_then_else (ne (symbol_ref "<Is_d_reg>") (const_int 0))
+ (if_then_else (match_test "<Is_d_reg>")
(const_string "neon_shift_1")
(const_string "neon_shift_3")))]
)
@@ -4182,7 +4182,7 @@ (define_insn "neon_vtrn<mode>_internal"
"TARGET_NEON"
"vtrn.<V_sz_elem>\t%<V_reg>0, %<V_reg>3"
[(set (attr "neon_type")
- (if_then_else (ne (symbol_ref "<Is_d_reg>") (const_int 0))
+ (if_then_else (match_test "<Is_d_reg>")
(const_string "neon_bp_simple")
(const_string "neon_bp_3cycle")))]
)
@@ -4209,7 +4209,7 @@ (define_insn "neon_vzip<mode>_internal"
"TARGET_NEON"
"vzip.<V_sz_elem>\t%<V_reg>0, %<V_reg>3"
[(set (attr "neon_type")
- (if_then_else (ne (symbol_ref "<Is_d_reg>") (const_int 0))
+ (if_then_else (match_test "<Is_d_reg>")
(const_string "neon_bp_simple")
(const_string "neon_bp_3cycle")))]
)
@@ -4236,7 +4236,7 @@ (define_insn "neon_vuzp<mode>_internal"
"TARGET_NEON"
"vuzp.<V_sz_elem>\t%<V_reg>0, %<V_reg>3"
[(set (attr "neon_type")
- (if_then_else (ne (symbol_ref "<Is_d_reg>") (const_int 0))
+ (if_then_else (match_test "<Is_d_reg>")
(const_string "neon_bp_simple")
(const_string "neon_bp_3cycle")))]
)
Index: gcc/config/arm/vfp.md
===================================================================
--- gcc/config/arm/vfp.md 2011-09-03 10:05:48.000000000 +0100
+++ gcc/config/arm/vfp.md 2011-09-13 18:38:08.000000000 +0100
@@ -173,7 +173,7 @@ (define_insn "*movdi_vfp"
(eq_attr "alternative" "3") (const_int 16)
(eq_attr "alternative" "9")
(if_then_else
- (eq (symbol_ref "TARGET_VFP_SINGLE")
(const_int 1))
+ (match_test "TARGET_VFP_SINGLE")
(const_int 8)
(const_int 4))]
(const_int 4)))
@@ -454,8 +454,7 @@ (define_insn "*movdf_vfp"
(set (attr "length") (cond [(eq_attr "alternative" "5,6,8") (const_int 8)
(eq_attr "alternative" "7")
(if_then_else
- (eq (symbol_ref "TARGET_VFP_SINGLE")
- (const_int 1))
+ (match_test "TARGET_VFP_SINGLE")
(const_int 8)
(const_int 4))]
(const_int 4)))
@@ -498,8 +497,7 @@ (define_insn "*thumb2_movdf_vfp"
(set (attr "length") (cond [(eq_attr "alternative" "5,6,8") (const_int 8)
(eq_attr "alternative" "7")
(if_then_else
- (eq (symbol_ref "TARGET_VFP_SINGLE")
- (const_int 1))
+ (match_test "TARGET_VFP_SINGLE")
(const_int 8)
(const_int 4))]
(const_int 4)))
Index: gcc/config/arm/thumb2.md
===================================================================
--- gcc/config/arm/thumb2.md 2011-09-03 10:05:48.000000000 +0100
+++ gcc/config/arm/thumb2.md 2011-09-13 18:38:08.000000000 +0100
@@ -951,7 +951,7 @@ (define_insn "*thumb2_cbz"
(if_then_else
(and (ge (minus (match_dup 1) (pc)) (const_int 2))
(le (minus (match_dup 1) (pc)) (const_int 128))
- (eq (symbol_ref ("which_alternative")) (const_int 0)))
+ (not (match_test "which_alternative")))
(const_int 2)
(const_int 8)))]
)
@@ -974,7 +974,7 @@ (define_insn "*thumb2_cbnz"
(if_then_else
(and (ge (minus (match_dup 1) (pc)) (const_int 2))
(le (minus (match_dup 1) (pc)) (const_int 128))
- (eq (symbol_ref ("which_alternative")) (const_int 0)))
+ (not (match_test "which_alternative")))
(const_int 2)
(const_int 8)))]
)
Index: gcc/config/arm/cortex-m4.md
===================================================================
--- gcc/config/arm/cortex-m4.md 2011-09-03 10:05:48.000000000 +0100
+++ gcc/config/arm/cortex-m4.md 2011-09-13 18:38:08.000000000 +0100
@@ -44,14 +44,14 @@ (define_insn_reservation "cortex_m4_load
(define_insn_reservation "cortex_m4_store1_1" 1
(and (and (eq_attr "tune" "cortexm4")
(eq_attr "type" "store1"))
- (ne (symbol_ref ("arm_address_offset_is_imm (insn)")) (const_int 0)))
+ (match_test "arm_address_offset_is_imm (insn)"))
"cortex_m4_a")
;; Other byte, half-word and word load is two cycles.
(define_insn_reservation "cortex_m4_store1_2" 2
(and (and (eq_attr "tune" "cortexm4")
(eq_attr "type" "store1"))
- (eq (symbol_ref ("arm_address_offset_is_imm (insn)")) (const_int 0)))
+ (not (match_test "arm_address_offset_is_imm (insn)")))
"cortex_m4_a*2")
(define_insn_reservation "cortex_m4_load2" 3
