This patch tweaks the movdi constraints for the PowerPC to use "^" or "$"
constraints instead of "?*". This allows the register allocator to more often
allocate DImode to a floating point/vector register when it is desirable to do
so.
I did a full Spec 2006 run with this patch installed, and most of the
benchmarks were neutral in terms of performance. The 482.sphinx3 benchmark had
a 2.5% performance boost with these patches. There were no benchmarks that
regressed with this patch.
I built bootstrap compilers and did make check with no regressions on:
1) Little endian power8, --with-cpu=power8
2) Big endian power8, --with-cpu=power8 (no 32-bit support)
3) Big endian power7, --with-cpu=power7 (both 32/64-bit support)
Can I check this patch into the trunk?
[gcc]
2016-11-18 Michael Meissner <meiss...@linux.vnet.ibm.com>
* config/rs6000/rs6000.md (movdi_internal32): Change FPR/VSX "?*"
load/store constraints to "^" if the instruction allows d-form
addressing or "$" if it only allows x-form addressing. Change
FPR/VSX move constraints to "^".
(movdi_internal64): Likewise.
[gcc/testsuite]
2016-11-18 Michael Meissner <meiss...@linux.vnet.ibm.com>
* gcc.target/powerpc/ppc-round2.c: Allow XSCVDPSXWS and XSCVDPUXWS
to be generated instead of FCTIWUZ or FCTIWZ.
--
Michael Meissner, IBM
IBM, M/S 2506R, 550 King Street, Littleton, MA 01460-6245, USA
email: meiss...@linux.vnet.ibm.com, phone: +1 (978) 899-4797
Index: gcc/config/rs6000/rs6000.md
===================================================================
--- gcc/config/rs6000/rs6000.md
(.../svn+ssh://meiss...@gcc.gnu.org/svn/gcc/trunk/gcc/config/rs6000)
(revision 242556)
+++ gcc/config/rs6000/rs6000.md (.../gcc/config/rs6000) (working copy)
@@ -8118,10 +8118,10 @@ (define_insn "p8_mfvsrd_4_disf"
(define_insn "*movdi_internal32"
[(set (match_operand:DI 0 "rs6000_nonimmediate_operand"
- "=Y, r, r, ?m, ?*d, ?*d,
- r, ?wY, ?Z, ?*wb, ?*wv, ?wi,
- ?wo, ?wo, ?wv, ?wi, ?wi, ?wv,
- ?wv")
+ "=Y, r, r, ^m, ^d, ^d,
+ r, ^wY, $Z, ^wb, $wv, ^wi,
+ *wo, *wo, *wv, *wi, *wi, *wv,
+ *wv")
(match_operand:DI 1 "input_operand"
"r, Y, r, d, m, d,
@@ -8195,9 +8195,9 @@ (define_split
(define_insn "*movdi_internal64"
[(set (match_operand:DI 0 "nonimmediate_operand"
"=Y, r, r, r, r, r,
- ?m, ?*d, ?*d, ?wY, ?Z, ?*wb,
- ?*wv, ?wi, ?wo, ?wo, ?wv, ?wi,
- ?wi, ?wv, ?wv, r, *h, *h,
+ ^m, ^d, ^d, ^Y, $Z, $wb,
+ $wv, ^wi, *wo, *wo, *wv, *wi,
+ *wi, *wv, *wv, r, *h, *h,
?*r, ?*wg, ?*r, ?*wj")
(match_operand:DI 1 "input_operand"
Index: gcc/testsuite/gcc.target/powerpc/ppc-round2.c
===================================================================
--- gcc/testsuite/gcc.target/powerpc/ppc-round2.c
(.../svn+ssh://meiss...@gcc.gnu.org/svn/gcc/trunk/gcc/testsuite/gcc.target/powerpc)
(revision 242556)
+++ gcc/testsuite/gcc.target/powerpc/ppc-round2.c
(.../gcc/testsuite/gcc.target/powerpc) (working copy)
@@ -5,8 +5,8 @@
/* { dg-options "-O2 -mcpu=power8" } */
/* { dg-final { scan-assembler-times "fcfid " 2 } } */
/* { dg-final { scan-assembler-times "fcfids " 2 } } */
-/* { dg-final { scan-assembler-times "fctiwuz " 2 } } */
-/* { dg-final { scan-assembler-times "fctiwz " 2 } } */
+/* { dg-final { scan-assembler-times "fctiwuz \|xscvdpuxws " 2 } } */
+/* { dg-final { scan-assembler-times "fctiwz \|xscvdpsxws " 2 } } */
/* { dg-final { scan-assembler-times "mfvsrd " 4 } } */
/* { dg-final { scan-assembler-times "mtvsrwa " 2 } } */
/* { dg-final { scan-assembler-times "mtvsrwz " 2 } } */
