Hi, This small patch series addresses a small number of issues around the `casesi_internal_mips16_<mode>' insn discovered in the course of recent development.
I have also made an attempt to factor the preparatory comparison and branch out as proper RTL operations from this insn, which is a relatively large assembly block. That however turned out to trigger an apparent bug elsewhere if the default case calls `__builtin_unreachable', causing both the branch and all the following instructions starting from the table jump to be optimized away, as if both legs of the branch were unreachable rather than just one. So I have backed out that fifth change until the nature of the problem has been investigated, however I do think we want to have it eventually as it should improve code scheduling in some cases. These changes have been successfully regression-tested all at once with the `mips-mti-linux-gnu' target and the little-endian MIPS16 o32 multilib only. Since the pattern is only ever used with MIPS16 code generation the changes do not apply to non-MIPS16 multilibs. See individual patch descriptions for details. Maciej
