Some quick remarks:
+(define_insn "kmovb"
+ [(set (match_operand:QI 0 "nonimmediate_operand" "=k,k")
+ (unspec:QI
+ [(match_operand:QI 1 "nonimmediate_operand" "r,km")]
+ UNSPEC_KMOV))]
+ "!(MEM_P (operands[0]) && MEM_P (operands[1])) && TARGET_AVX512DQ"
+ "@
+ kmovb\t{%k1, %0|%0, %k1}
+ kmovb\t{%1, %0|%0, %1}";
+ [(set_attr "mode" "QI")
+ (set_attr "type" "mskmov")
+ (set_attr "prefix" "vex")])
+
+(define_insn "kmovd"
+ [(set (match_operand:SI 0 "nonimmediate_operand" "=k,k")
+ (unspec:SI
+ [(match_operand:SI 1 "nonimmediate_operand" "r,km")]
+ UNSPEC_KMOV))]
+ "!(MEM_P (operands[0]) && MEM_P (operands[1])) && TARGET_AVX512BW"
+ "@
+ kmovd\t{%k1, %0|%0, %k1}
+ kmovd\t{%1, %0|%0, %1}";
+ [(set_attr "mode" "SI")
+ (set_attr "type" "mskmov")
+ (set_attr "prefix" "vex")])
+
+(define_insn "kmovq"
+ [(set (match_operand:DI 0 "nonimmediate_operand" "=k,k,km")
+ (unspec:DI
+ [(match_operand:DI 1 "nonimmediate_operand" "r,km,k")]
+ UNSPEC_KMOV))]
+ "!(MEM_P (operands[0]) && MEM_P (operands[1])) && TARGET_AVX512BW"
+ "@
+ kmovq\t{%k1, %0|%0, %k1}
+ kmovq\t{%1, %0|%0, %1}
+ kmovq\t{%1, %0|%0, %1}";
+ [(set_attr "mode" "DI")
+ (set_attr "type" "mskmov")
+ (set_attr "prefix" "vex")])
- kmovd (and existing kmovw) should be using register_operand for
opreand 0. In this case, there is no need for MEM_P checks at all.
- In the insn constraint, pease check TARGET_AVX before checking MEM_P.
- please put these definitions above corresponding *mov??_internal patterns.
+// case USI_FTYPE_UQI:
+// case USI_FTYPE_UHI:
No commented-out code without a good reason, please.
Uros.
