Richard Earnshaw wrote: > On 10/11/16 17:19, Wilco Dijkstra wrote: > > Improve the logic when setting max_insns_skipped. Limit the maximum size > > of IT > > to MAX_INSN_PER_IT_BLOCK as otherwise multiple IT instructions are needed, > > increasing codesize. > > You don't provide any information about what benefits this brings.
It reduces codesize and improves performance as you avoid emitting a second IT instruction for sequences of more than 4 conditional instructions. > > Given 4 works well for Thumb-2, use the same limit for ARM > > for consistency. > > Why? Logic might suggest that given thumb has to execute an IT > instruction first, then allowing ARM to have one more conditional > instruction is the best answer. Long conditional sequences are slow on modern cores - the value 6 for max_insns_skipped is a few decades out of date as it was meant for ARM2! Even with -Os the performance loss for larger values is not worth the small codesize gain (there are many better options to reduce codesize that actually improve performance at the same time). So using the same code generation heuristics for ARM and Thumb-2 is a good idea. Wilco
