The second patch updates the Cortex-A57 scheduler now that we can differentiate
between shifts and bitfield inserts. The Cortex-A57 Software Optimization Guide
indicates that BFM operations use the integer multi-cycle pipeline, while ARM
UXTB/H instructions use the Integer 1 or Integer 0 pipelines, so swap the bfm
and extend reservations. This results in minor scheduling differences.
I think the XGene-1 scheduler might need a similar change as currently all
AArch64
shifts are modelled as 2-cycle operations.
ChangeLog:
2016-11-10 Wilco Dijkstra <wdijk...@arm.com>
* config/arm/cortex-a57.md (cortex_a57_alu): Move extend here, move
bfm...
(cortex_a57_alu_shift): ...here.
--
diff --git a/gcc/config/arm/cortex-a57.md b/gcc/config/arm/cortex-a57.md
index
da461846baa5b28ce3d9c9f731dbfd7becb31a85..63072509e50375929f75c44af900a4803a6285f3
100644
--- a/gcc/config/arm/cortex-a57.md
+++ b/gcc/config/arm/cortex-a57.md
@@ -297,7 +297,7 @@
(eq_attr "type" "alu_imm,alus_imm,logic_imm,logics_imm,\
alu_sreg,alus_sreg,logic_reg,logics_reg,\
adc_imm,adcs_imm,adc_reg,adcs_reg,\
- adr,bfm,bfx,clz,rbit,rev,alu_dsp_reg,\
+ adr,bfx,extend,clz,rbit,rev,alu_dsp_reg,\
rotate_imm,shift_imm,shift_reg,\
mov_imm,mov_reg,\
mvn_imm,mvn_reg,\
@@ -307,7 +307,7 @@
;; ALU ops with immediate shift
(define_insn_reservation "cortex_a57_alu_shift" 3
(and (eq_attr "tune" "cortexa57")
- (eq_attr "type" "extend,\
+ (eq_attr "type" "bfm,\
alu_shift_imm,alus_shift_imm,\
crc,logic_shift_imm,logics_shift_imm,\
mov_shift,mvn_shift"))
