On Mon, Oct 17, 2016 at 05:15:21PM +0100, Kyrill Tkachov wrote: > Hi all, > > For the attached testcase the code ends up trying to extract bits outside the > range of the normal register widths. The aarch64 patterns for ubfz and tbnz > end up accepting such operands and emitting invalid assembly > such as 'ubfx x18,x2,192,32' > > The solution is to add proper predicates and guards to the operands of the > zero_extract operations that are going on. I had a look at all the other > patterns in aarch64 that generate/use zero_extract and they all have guards > on their > operands in one form or another to avoid them accessing an area that is out > of range. > > With this patch the testcase compiles and assembles fine. > > Bootstrapped and tested on aarch64-none-linux-gnu. > > Ok for trunk?
Ok, sorry for the delay on review. Thanks, James > 2016-10-17 Kyrylo Tkachov <kyrylo.tkac...@arm.com> > > PR target/77822 > * config/aarch64/aarch64.md (*tb<optab><mode>1): Use > aarch64_simd_shift_imm_<mode> predicate for operand 1. > (<optab>, ANY_EXTRACT): Use tighter predicates on operands 2 and 3 > to restrict them to an appropriate range and add FAIL check if the > region they specify is out of range. Delete useless constraint > strings. > (*<optab><mode>, ANY_EXTRACT): Add appropriate predicates on operands > 2 and 3 to restrict their range and add pattern predicate. >
