Hi,
When using a callee-saved register to save the frame pointer the Thumb-1
prologue fails to save the callee-saved register before that. For ARM and
Thumb-2 targets the frame pointer is handled as a special case but nothing is
done for Thumb-1 targets. This patch adds the same logic for Thumb-1 targets.
ChangeLog entries are as follow:
*** gcc/ChangeLog ***
2016-11-02 Thomas Preud'homme <thomas.preudho...@arm.com>
PR target/77904
* config/arm/arm.c (thumb1_compute_save_reg_mask): mark frame pointer
in save register mask if it is needed.
*** gcc/testsuite/ChangeLog ***
2016-11-02 Thomas Preud'homme <thomas.preudho...@arm.com>
PR target/77904
* gcc.target/arm/pr77904.c: New test.
Testing: Testsuite shows no regression when run with arm-none-eabi GCC
cross-compiler for Cortex-M0 target.
Is this ok for trunk?
Best regards,
Thomas
diff --git a/gcc/config/arm/arm.c b/gcc/config/arm/arm.c
index dd8d5e5db8ca50daab648e58df290969aa794862..c7bf3320a3db5dfc4f33ae145ff2e5f239d6c0f9 100644
--- a/gcc/config/arm/arm.c
+++ b/gcc/config/arm/arm.c
@@ -19495,6 +19495,10 @@ thumb1_compute_save_reg_mask (void)
if (df_regs_ever_live_p (reg) && callee_saved_reg_p (reg))
mask |= 1 << reg;
+ /* Handle the frame pointer as a special case. */
+ if (frame_pointer_needed)
+ mask |= 1 << HARD_FRAME_POINTER_REGNUM;
+
if (flag_pic
&& !TARGET_SINGLE_PIC_BASE
&& arm_pic_register != INVALID_REGNUM
diff --git a/gcc/testsuite/gcc.target/arm/pr77904.c b/gcc/testsuite/gcc.target/arm/pr77904.c
new file mode 100644
index 0000000000000000000000000000000000000000..76728c07e73350ce44160cabff3dd2fa7a6ef021
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/pr77904.c
@@ -0,0 +1,45 @@
+/* { dg-do run } */
+/* { dg-options "-O2" } */
+
+__attribute__ ((noinline, noclone)) void
+clobber_sp (void)
+{
+ __asm volatile ("" : : : "sp");
+}
+
+int
+main (void)
+{
+ int ret;
+
+ __asm volatile ("mov\tr4, #0xf4\n\t"
+ "mov\tr5, #0xf5\n\t"
+ "mov\tr6, #0xf6\n\t"
+ "mov\tr7, #0xf7\n\t"
+ "mov\tr0, #0xf8\n\t"
+ "mov\tr8, r0\n\t"
+ "mov\tr0, #0xfa\n\t"
+ "mov\tr10, r0"
+ : : : "r0", "r4", "r5", "r6", "r7", "r8", "r10");
+ clobber_sp ();
+
+ __asm volatile ("cmp\tr4, #0xf4\n\t"
+ "bne\tfail\n\t"
+ "cmp\tr5, #0xf5\n\t"
+ "bne\tfail\n\t"
+ "cmp\tr6, #0xf6\n\t"
+ "bne\tfail\n\t"
+ "cmp\tr7, #0xf7\n\t"
+ "bne\tfail\n\t"
+ "mov\tr0, r8\n\t"
+ "cmp\tr0, #0xf8\n\t"
+ "bne\tfail\n\t"
+ "mov\tr0, r10\n\t"
+ "cmp\tr0, #0xfa\n\t"
+ "bne\tfail\n\t"
+ "mov\t%0, #1\n"
+ "fail:\n\t"
+ "sub\tr0, #1"
+ : "=r" (ret) : :);
+ return ret;
+}
