On 10/18/16 10:36, Christophe Lyon wrote:
>
> I am seeing a lot of regressions since this patch was committed:
> http://people.linaro.org/~christophe.lyon/cross-validation/gcc/trunk/241273/report-build-info.html
>
> (you can click on "REGRESSED" to see the list of regressions, "sum"
> and "log" to download
> the corresponding .sum/.log)
>
> Thanks,
>
> Christophe
>
Oh, sorry, I have completely missed that.
Unfortunately I have tested one of the good combinations.
I have not considered the case that in and out could be
the same register. But that happens here.
This should solve it.
Can you give it a try?
Thanks
Bernd.
2016-10-18 Bernd Edlinger <bernd.edlin...@hotmail.de>
* config/arm/arm.c (arm_emit_coreregs_64bit_shift): Clear the result
register only if "in" and "out" are different registers.
--- gcc/config/arm/arm.c.orig 2016-10-17 11:00:34.045673223 +0200
+++ gcc/config/arm/arm.c 2016-10-18 14:53:06.710101327 +0200
@@ -29218,8 +29218,10 @@ arm_emit_coreregs_64bit_shift (enum rtx_
/* Clearing the out register in DImode first avoids lots
of spilling and results in less stack usage.
- Later this redundant insn is completely removed. */
- emit_insn (SET (out, const0_rtx));
+ Later this redundant insn is completely removed.
+ Do that only if "in" and "out" are different registers. */
+ if (REG_P (out) && REG_P (in) && REGNO (out) != REGNO (in))
+ emit_insn (SET (out, const0_rtx));
emit_insn (SET (out_down, LSHIFT (code, in_down, amount)));
emit_insn (SET (out_down,
ORR (REV_LSHIFT (code, in_up, reverse_amount),
@@ -29231,11 +29233,14 @@ arm_emit_coreregs_64bit_shift (enum rtx_
/* Shifts by a constant greater than 31. */
rtx adj_amount = GEN_INT (INTVAL (amount) - 32);
- emit_insn (SET (out, const0_rtx));
+ if (REG_P (out) && REG_P (in) && REGNO (out) != REGNO (in))
+ emit_insn (SET (out, const0_rtx));
emit_insn (SET (out_down, SHIFT (code, in_up, adj_amount)));
if (code == ASHIFTRT)
emit_insn (gen_ashrsi3 (out_up, in_up,
GEN_INT (31)));
+ else
+ emit_insn (SET (out_up, const0_rtx));
}
}
else
