Hi Eric.
+(define_insn "*plus_sltu<W:mode>_vis3"
+ [(set (match_operand:W 0 "register_operand" "=r")
+ (plus:W (ltu:W (match_operand 2 "icc_register_operand" "X")
+ (const_int 0))
+ (match_operand:W 1 "arith_operand" "rI")))]
+ "TARGET_ARCH64 && TARGET_VIS3
+ && (GET_MODE (operands[2]) == CCXmode || GET_MODE (operands[2]) ==
CCXCmode)"
+ "addxc\t%%g0, %1, %0"
+ [(set_attr "type" "ialuX")])
[...]
+(define_insn "*minus_neg_sltu<W:mode>_subxc"
+ [(set (match_operand:W 0 "register_operand" "=r")
+ (minus:W (neg:W (ltu:W (match_operand 2 "icc_register_operand" "X")
+ (const_int 0)))
+ (match_operand:W 1 "arith_operand" "rI")))]
+ "TARGET_ARCH64 && TARGET_SUBXC
+ && (GET_MODE (operands[2]) == CCXmode || GET_MODE (operands[2]) ==
CCXCmode)"
+ "subxc\t%%g0, %1, %0"
[... etc ...]
Note that the ADDXC, ADDXCCC, SUBXC and SUBXCCC instructions do not
support immediate operands. Hence the patch breaks vis3-enabling arches
and niagara-7.
(Yes, ADXCC and SUBXCC both support immediate operands, it can be
confusing :/)
