>From: Christophe Lyon [christophe.l...@linaro.org]
>Sent: Monday, October 03, 2016 12:05 AM
>To: Doug Gilmore
>Cc: gcc-patches@gcc.gnu.org
>Subject: Re: Fix PR tree-optimization/77808, ICE in
>duplicate_ssa_name_ptr_info, at tree-ssanames.c:630 starting with r240439
>
>On 2 October 2016 at 23:05, Doug Gilmore <doug.gilm...@imgtec.com> wrote:
>> Hi Christophe,
>>
>>> From: Christophe Lyon [christophe.l...@linaro.org]
>>> Sent: Saturday, October 01, 2016 7:57 AM
>>> To: Doug Gilmore
>>> Cc: gcc-patches@gcc.gnu.org
>>> Subject: Re: Fix PR tree-optimization/77808, ICE in
>>> duplicate_ssa_name_ptr_info, at tree-ssanames.c:630 starting with r240439
>>>
>>> Hi Doug,
>>>
>>> ...
>>> I can confirm that your patch fixes the ICE I was seeing.
>>>
>>> However, the new testcase does not pass on low end
>>> architectures:
>>> cc1: warning: -fprefetch-loop-arrays not supported for this target
>>> (try -march switches)
>>>
>>> Can you add a guard?
>>>
>>> Thanks,
>>>
>>> Christophe
>> I updated the test to only run on X86, MIPS and AARCH64. Is that OK?
>>
>
>I'm afraid not.
>
>The ICE occurred on some arm targets. By "low end" I meant armv5t for
>example, as opposed to armv7t.
>Is there a suitable effective target?
I'll need to investigate that. BTW, gcc.dg/pr53550.c contains:
/* PR tree-optimization/53550 */
/* { dg-do compile } */
/* { dg-options "-O2 -fprefetch-loop-arrays -w" } */
int *
foo (int *x)
{
int *a = x + 10, *b = x, *c = a;
while (b != c)
*--c = *b++;
return x;
}
Is it also failing on armv5t? I suppose it would.
Thanks,
Doug
>
>Thanks,
>
>Christophe
>
>> Thanks,
>>
>> Doug
