On 08/05/2016 08:04 PM, Segher Boessenkool wrote: > On Fri, Aug 05, 2016 at 04:27:36PM -0500, Pat Haugen wrote: >> On 08/02/2016 03:15 PM, Segher Boessenkool wrote: >>> On Tue, Aug 02, 2016 at 03:03:42PM -0500, Pat Haugen wrote: >>>> On 07/29/2016 10:47 AM, Kelvin Nilsen wrote: >>>>> + "xsxexpdp %0,%x1" >>>>> + [(set_attr "type" "fp")]) >>>> >>>> Type should be 'integer'. >>> >>> It has VSX regs as input, integer is worse than fpsimple here, I think? >>> Or vecsimple, that seems better yes. >> >> It's a 2 cycle op that executes in the ALU pipe, just like other integer >> ops. vecsimple would be worse since those consume a superslice, which this >> op doesn't. >> > > Ah yes. But why not fpsimple? It schedules the same as e.g. fmr and > fabs? >
The subtle difference is that since it has a GPR target it does not restrict a tuple (3 insns) from being dispatched to a superslice, whereas fpsimple ops do. -Pat
