On Wed, Jul 20, 2016 at 06:00:46PM +0100, Jiong Wang wrote:
> On 07/07/16 17:15, Jiong Wang wrote:
> >This patch add ARMv8.2-A FP16 two operands vector intrinsics.
>
> The updated patch resolve the conflict with
>
> https://gcc.gnu.org/ml/gcc-patches/2016-06/msg00309.html
>
> The change is to let aarch64_emit_approx_div return false for
> V4HFmode and V8HFmode.
As with patch 2/14, please rewrite this hunk:
> diff --git a/gcc/config/aarch64/aarch64.c b/gcc/config/aarch64/aarch64.c
> index
> 5ed633542efe58763d68fd9bfbb478ae6ef569c3..a7437c04eb936a5e3ebd0bc77eb4afd8c052df28
> 100644
> --- a/gcc/config/aarch64/aarch64.c
> +++ b/gcc/config/aarch64/aarch64.c
> @@ -7717,6 +7717,10 @@ bool
> aarch64_emit_approx_div (rtx quo, rtx num, rtx den)
> {
> machine_mode mode = GET_MODE (quo);
> +
> + if (mode == V4HFmode || mode == V8HFmode)
> + return false;
> +
To:
if (GET_MODE_INNER (mode) == HFmode)
return false;
Otherwise, this patch is OK for trunk.
Thanks,
James
> gcc/
> 2016-07-20 Jiong Wang<jiong.w...@arm.com>
>
> * config/aarch64/aarch64-simd-builtins.def: Register new builtins.
> * config/aarch64/aarch64-simd.md
> (aarch64_rsqrts<mode>): Extend to HF modes.
> (fabd<mode>3): Likewise.
> (<FCVT_F2FIXED:fcvt_fixed_insn><VHSDF_SDF:mode>3): Likewise.
> (<FCVT_FIXED2F:fcvt_fixed_insn><VHSDI_SDI:mode>3): Likewise.
> (aarch64_<maxmin_uns>p<mode>): Likewise.
> (<su><maxmin><mode>3): Likewise.
> (<maxmin_uns><mode>3): Likewise.
> (<fmaxmin><mode>3): Likewise.
> (aarch64_faddp<mode>): Likewise.
> (aarch64_fmulx<mode>): Likewise.
> (aarch64_frecps<mode>): Likewise.
> (*aarch64_fac<optab><mode>): Rename to aarch64_fac<optab><mode>.
> (add<mode>3): Extend to HF modes.
> (sub<mode>3): Likewise.
> (mul<mode>3): Likewise.
> (div<mode>3): Likewise.
> (*div<mode>3): Likewise.
> * config/aarch64/aarch64.c (aarch64_emit_approx_div): Return
> false for V4HF and V8HF.
> * config/aarch64/iterators.md (VDQ_HSDI, VSDQ_HSDI): New mode
> iterator.
> * config/aarch64/arm_neon.h (vadd_f16): Likewise.
> (vaddq_f16): Likewise.
> (vabd_f16): Likewise.
> (vabdq_f16): Likewise.
> (vcage_f16): Likewise.
> (vcageq_f16): Likewise.
> (vcagt_f16): Likewise.
> (vcagtq_f16): Likewise.
> (vcale_f16): Likewise.
> (vcaleq_f16): Likewise.
> (vcalt_f16): Likewise.
> (vcaltq_f16): Likewise.
> (vceq_f16): Likewise.
> (vceqq_f16): Likewise.
> (vcge_f16): Likewise.
> (vcgeq_f16): Likewise.
> (vcgt_f16): Likewise.
> (vcgtq_f16): Likewise.
> (vcle_f16): Likewise.
> (vcleq_f16): Likewise.
> (vclt_f16): Likewise.
> (vcltq_f16): Likewise.
> (vcvt_n_f16_s16): Likewise.
> (vcvtq_n_f16_s16): Likewise.
> (vcvt_n_f16_u16): Likewise.
> (vcvtq_n_f16_u16): Likewise.
> (vcvt_n_s16_f16): Likewise.
> (vcvtq_n_s16_f16): Likewise.
> (vcvt_n_u16_f16): Likewise.
> (vcvtq_n_u16_f16): Likewise.
> (vdiv_f16): Likewise.
> (vdivq_f16): Likewise.
> (vdup_lane_f16): Likewise.
> (vdup_laneq_f16): Likewise.
> (vdupq_lane_f16): Likewise.
> (vdupq_laneq_f16): Likewise.
> (vdups_lane_f16): Likewise.
> (vdups_laneq_f16): Likewise.
> (vmax_f16): Likewise.
> (vmaxq_f16): Likewise.
> (vmaxnm_f16): Likewise.
> (vmaxnmq_f16): Likewise.
> (vmin_f16): Likewise.
> (vminq_f16): Likewise.
> (vminnm_f16): Likewise.
> (vminnmq_f16): Likewise.
> (vmul_f16): Likewise.
> (vmulq_f16): Likewise.
> (vmulx_f16): Likewise.
> (vmulxq_f16): Likewise.
> (vpadd_f16): Likewise.
> (vpaddq_f16): Likewise.
> (vpmax_f16): Likewise.
> (vpmaxq_f16): Likewise.
> (vpmaxnm_f16): Likewise.
> (vpmaxnmq_f16): Likewise.
> (vpmin_f16): Likewise.
> (vpminq_f16): Likewise.
> (vpminnm_f16): Likewise.
> (vpminnmq_f16): Likewise.
> (vrecps_f16): Likewise.
> (vrecpsq_f16): Likewise.
> (vrsqrts_f16): Likewise.
> (vrsqrtsq_f16): Likewise.
> (vsub_f16): Likewise.
> (vsubq_f16): Likewise.
