RE: [PATCH 1/7] SMS remove dependence on doloop: Use loop induction variable analysis in SMS pass

[Shiva Chen]

Hi, Jeff

Thanks for the tips.
I update the patches to pass regression test and x86 bootstrap when sms enabled 
as default.

Shiva

-----Original Message-----
From: Jeff Law [mailto:l...@redhat.com] 
Sent: Thursday, June 23, 2016 12:43 AM
To: Shiva Chen; GCC Patches; bschm...@redhat.com; Shiva Chen
Subject: Re: [PATCH 1/7] SMS remove dependence on doloop: Use loop induction 
variable analysis in SMS pass

On 05/05/2016 12:01 AM, Shiva Chen wrote:
> Hi,
>
> SMS transformation would change the kernel loop iteration count.
> To do this, SMS pass will find the register contain loop count and 
> generate the instructions to adjust loop count.
>
> Currently, SMS will try to find count_reg by recognizing doloop_end 
> pattern which means if the target didn't define doloop_end pattern or 
> the loop not suitable for doloop optimization, SMS pass won't active.
>
> The patch use induction variable analysis to find count_reg instead of 
> find doloop_end pattern.
So these patches need to be bootstrapped and regression tested.  Since SMS is 
not the default on any major platforms, I would recommend first hacking SMS to 
be enabled by default.  That isn't a patch you're going to submit, but instead 
it allows you to do bootstrap and regression testing on x86_64, ppc64 or 
whatever desktop/server machines you have access to.

I did that with patch #1 just to see what would happen and I get an assert 
triggered in generate_prolog_epilog:

       gcc_assert (REG_P (sub_reg));

Where sub_reg and count_reg are:

(subreg:SI (reg:DI 146 [ ivtmp.11 ]) 0)


AFAICT (reg:DI 146) is the actual IV, but the test actually occurs in
SImode:


(insn 80 79 82 7 (parallel [
             (set (reg:DI 146 [ ivtmp.11 ])
                 (plus:DI (reg:DI 146 [ ivtmp.11 ])
                     (const_int -1 [0xffffffffffffffff])))
             (clobber (reg:CC 17 flags))
         ]) 212 {*adddi_1}
      (expr_list:REG_UNUSED (reg:CC 17 flags)
         (nil)))

(insn 82 80 83 7 (set (reg:CCGOC 17 flags)
         (compare:CCGOC (subreg:SI (reg:DI 146 [ ivtmp.11 ]) 0)
             (const_int 0 [0]))) 
../../../../gcc/libstdc++-v3/libsupc++/hash_bytes.cc:54 3 {*cmpsi_ccno_1}
      (nil))

(jump_insn 83 82 84 7 (set (pc)
         (if_then_else (ge (reg:CCGOC 17 flags)
                 (const_int 0 [0]))
             (label_ref:DI 81)
             (pc))) 
../../../../gcc/libstdc++-v3/libsupc++/hash_bytes.cc:54 635 {*jcc_1}
      (expr_list:REG_DEAD (reg:CCGOC 17 flags)
         (int_list:REG_BR_PROB 8500 (nil)))
  -> 81)


So you either need to be filtering out cases where the IV is in a 
different mode than its test or handling SUBREGs better throughout the code.

I haven't looked deeply at any of the patches yet.  I won't until 
they're in better shape from a correctness standpoint.

Jeff

0001-Use-loop-induction-variable-analysis-in-SMS-pass.patch
Description: 0001-Use-loop-induction-variable-analysis-in-SMS-pass.patch

0002-Use-get_simple_loop_desc-to-get-loop-iteration-count.patch
Description: 0002-Use-get_simple_loop_desc-to-get-loop-iteration-count.patch

0003-Update-loop-versioning-for-the-loop-with-step-1.patch
Description: 0003-Update-loop-versioning-for-the-loop-with-step-1.patch

0004-update-kernel-loop-iteration-adjustment-instruction-.patch
Description: 0004-update-kernel-loop-iteration-adjustment-instruction-.patch

0005-update-generate_prolog_epilog-for-the-case-without-d.patch
Description: 0005-update-generate_prolog_epilog-for-the-case-without-d.patch

0006-skip-the-loop-if-the-loop-size-too-small.patch
Description: 0006-skip-the-loop-if-the-loop-size-too-small.patch

0007-To-identify-READ_WRITE_REG-as-loop-induction-variabl.patch
Description: 0007-To-identify-READ_WRITE_REG-as-loop-induction-variabl.patch

0008-Fix-True-dependence-by-CC-register-wrap-around-and-c.patch
Description: 0008-Fix-True-dependence-by-CC-register-wrap-around-and-c.patch