The following patch fixes
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=71621
The patch was successfully bootstrapped and tested on x86/x86-64.
Committed as rev. 238178
Index: ChangeLog
===================================================================
--- ChangeLog (revision 238175)
+++ ChangeLog (working copy)
@@ -1,3 +1,9 @@
+2016-07-08 Vladimir Makarov <vmaka...@redhat.com>
+
+ PR rtl-optimization/71621
+ * lra-constraints.c (process_alt_operands): Check combination of
+ reg class and mode.
+
2016-06-25 Jason Merrill <ja...@redhat.com>
Richard Biener <rguent...@suse.de>
Index: testsuite/ChangeLog
===================================================================
--- testsuite/ChangeLog (revision 238175)
+++ testsuite/ChangeLog (working copy)
@@ -1,3 +1,9 @@
+2016-07-08 Vladimir Makarov <vmaka...@redhat.com>
+
+ PR rtl-optimization/71621
+ * gcc.target/i386/pr71621-1.c: New.
+ * gcc.target/i386/pr71621-2.c: New.
+
2016-07-08 Cesar Philippidis <ce...@codesourcery.com>
* gfortran.dg/goacc/pr71704.f90: New test.
Index: lra-constraints.c
===================================================================
--- lra-constraints.c (revision 237993)
+++ lra-constraints.c (working copy)
@@ -2261,6 +2261,41 @@ process_alt_operands (int only_alternati
goto fail;
}
+ if (this_alternative != NO_REGS)
+ {
+ HARD_REG_SET available_regs;
+
+ COPY_HARD_REG_SET (available_regs,
+ reg_class_contents[this_alternative]);
+ AND_COMPL_HARD_REG_SET
+ (available_regs,
+ ira_prohibited_class_mode_regs[this_alternative][mode]);
+ AND_COMPL_HARD_REG_SET (available_regs, lra_no_alloc_regs);
+ if (hard_reg_set_empty_p (available_regs))
+ {
+ /* There are no hard regs holding a value of given
+ mode. */
+ if (offmemok)
+ {
+ this_alternative = NO_REGS;
+ if (lra_dump_file != NULL)
+ fprintf (lra_dump_file,
+ " %d Using memory because of"
+ " a bad mode: reject+=2\n",
+ nop);
+ reject += 2;
+ }
+ else
+ {
+ if (lra_dump_file != NULL)
+ fprintf (lra_dump_file,
+ " alt=%d: Wrong mode -- refuse\n",
+ nalt);
+ goto fail;
+ }
+ }
+ }
+
/* If not assigned pseudo has a class which a subset of
required reg class, it is a less costly alternative
as the pseudo still can get a hard reg of necessary
Index: testsuite/gcc.target/i386/pr71621-1.c
===================================================================
--- testsuite/gcc.target/i386/pr71621-1.c (revision 0)
+++ testsuite/gcc.target/i386/pr71621-1.c (working copy)
@@ -0,0 +1,31 @@
+/* { dg-do compile } */
+/* { dg-options "-O2 -w -ftree-vectorize -mavx2" } */
+
+int cn;
+int *li;
+
+void
+y8 (void)
+{
+ int gv;
+ int *be = &gv;
+ short int v4 = 2;
+
+ while (*li != 0)
+ {
+ int sy;
+ for (sy = 0; sy < 5; ++sy)
+ {
+ int **t6 = &be;
+ gv |= sy ? 0 : v4;
+ if (gv != 0)
+ ++gv;
+ t6 = &cn;
+ if (gv != 0)
+ *t6 = 0;
+ }
+ for (gv = 0; gv < 24; ++gv)
+ v4 |= 1 <= 1 % 0;
+ ++(*li);
+ }
+}
Index: testsuite/gcc.target/i386/pr71621-2.c
===================================================================
--- testsuite/gcc.target/i386/pr71621-2.c (revision 0)
+++ testsuite/gcc.target/i386/pr71621-2.c (working copy)
@@ -0,0 +1,39 @@
+/* { dg-do compile } */
+/* { dg-options "-O3 -mavx2" } */
+
+int hf, sv, zz, aj;
+
+void
+dn (int xb, int bl)
+{
+ while (zz < 1)
+ {
+ if (xb == 0)
+ goto mr;
+
+ while (bl < 3)
+ {
+ int d3;
+ unsigned char vh;
+ unsigned char *fj = &vh;
+
+ mr:
+ while (bl < 1)
+ {
+ hf += vh;
+ ++bl;
+ }
+ if (xb == 0)
+ zz = bl;
+ if (d3 == 0)
+ return;
+ while (sv < 1)
+ {
+ --vh;
+ aj += vh;
+ ++sv;
+ }
+ }
+ sv = 0;
+ }
+}
