This patch add ARMv8.2-A FP16 three operands scalar intrinsics.
gcc/
2016-07-07 Jiong Wang <jiong.w...@arm.com>
* config/aarch64/aarch64-simd-builtins.def: Register new builtins.
* config/aarch64/aarch64.md (fma): New for HF.
(fnma): Likewise.
* config/aarch64/arm_fp16.h (vfmah_f16): New.
(vfmsh_f16): Likewise.
>From 292838908f82ed8b1e0dbf79e451cbb82841f9ed Mon Sep 17 00:00:00 2001
From: Jiong Wang <jiong.w...@arm.com>
Date: Thu, 9 Jun 2016 11:05:27 +0100
Subject: [PATCH 09/14] [9/14] ARMv8.2 FP16 three operands scalar intrinsics
---
gcc/config/aarch64/aarch64-simd-builtins.def | 2 ++
gcc/config/aarch64/aarch64.md | 21 +++++++++++----------
gcc/config/aarch64/arm_fp16.h | 14 ++++++++++++++
3 files changed, 27 insertions(+), 10 deletions(-)
diff --git a/gcc/config/aarch64/aarch64-simd-builtins.def b/gcc/config/aarch64/aarch64-simd-builtins.def
index b32fdfe..bc5eda6 100644
--- a/gcc/config/aarch64/aarch64-simd-builtins.def
+++ b/gcc/config/aarch64/aarch64-simd-builtins.def
@@ -422,8 +422,10 @@
/* Implemented by fma<mode>4. */
BUILTIN_VHSDF (TERNOP, fma, 4)
+ VAR1 (TERNOP, fma, 4, hf)
/* Implemented by fnma<mode>4. */
BUILTIN_VHSDF (TERNOP, fnma, 4)
+ VAR1 (TERNOP, fnma, 4, hf)
/* Implemented by aarch64_simd_bsl<mode>. */
BUILTIN_VDQQH (BSL_P, simd_bsl, 0)
diff --git a/gcc/config/aarch64/aarch64.md b/gcc/config/aarch64/aarch64.md
index 81a4f20..5664fd1 100644
--- a/gcc/config/aarch64/aarch64.md
+++ b/gcc/config/aarch64/aarch64.md
@@ -4493,23 +4493,24 @@
;; fma - no throw
(define_insn "fma<mode>4"
- [(set (match_operand:GPF 0 "register_operand" "=w")
- (fma:GPF (match_operand:GPF 1 "register_operand" "w")
- (match_operand:GPF 2 "register_operand" "w")
- (match_operand:GPF 3 "register_operand" "w")))]
+ [(set (match_operand:GPF_F16 0 "register_operand" "=w")
+ (fma:GPF_F16 (match_operand:GPF_F16 1 "register_operand" "w")
+ (match_operand:GPF_F16 2 "register_operand" "w")
+ (match_operand:GPF_F16 3 "register_operand" "w")))]
"TARGET_FLOAT"
"fmadd\\t%<s>0, %<s>1, %<s>2, %<s>3"
- [(set_attr "type" "fmac<s>")]
+ [(set_attr "type" "fmac<stype>")]
)
(define_insn "fnma<mode>4"
- [(set (match_operand:GPF 0 "register_operand" "=w")
- (fma:GPF (neg:GPF (match_operand:GPF 1 "register_operand" "w"))
- (match_operand:GPF 2 "register_operand" "w")
- (match_operand:GPF 3 "register_operand" "w")))]
+ [(set (match_operand:GPF_F16 0 "register_operand" "=w")
+ (fma:GPF_F16
+ (neg:GPF_F16 (match_operand:GPF_F16 1 "register_operand" "w"))
+ (match_operand:GPF_F16 2 "register_operand" "w")
+ (match_operand:GPF_F16 3 "register_operand" "w")))]
"TARGET_FLOAT"
"fmsub\\t%<s>0, %<s>1, %<s>2, %<s>3"
- [(set_attr "type" "fmac<s>")]
+ [(set_attr "type" "fmac<stype>")]
)
(define_insn "fms<mode>4"
diff --git a/gcc/config/aarch64/arm_fp16.h b/gcc/config/aarch64/arm_fp16.h
index 21edc65..4b7c2dd 100644
--- a/gcc/config/aarch64/arm_fp16.h
+++ b/gcc/config/aarch64/arm_fp16.h
@@ -560,6 +560,20 @@ vsubh_f16 (float16_t __a, float16_t __b)
return __a - __b;
}
+/* ARMv8.2-A FP16 three operands scalar intrinsics. */
+
+__extension__ static __inline float16_t __attribute__ ((__always_inline__))
+vfmah_f16 (float16_t __a, float16_t __b, float16_t __c)
+{
+ return __builtin_aarch64_fmahf (__b, __c, __a);
+}
+
+__extension__ static __inline float16_t __attribute__ ((__always_inline__))
+vfmsh_f16 (float16_t __a, float16_t __b, float16_t __c)
+{
+ return __builtin_aarch64_fnmahf (__b, __c, __a);
+}
+
#pragma GCC pop_options
#endif
--
2.5.0
