On Mon, Jun 27, 2016 at 04:46:00PM -0500, Pat Haugen wrote: > On 06/22/2016 02:10 PM, Segher Boessenkool wrote: > >> Index: config/rs6000/htm.md > >> =================================================================== > >> --- config/rs6000/htm.md (revision 237621) > >> +++ config/rs6000/htm.md (working copy) > >> @@ -72,7 +72,8 @@ (define_insn "*tabort" > >> (set (match_operand:BLK 2) (unspec:BLK [(match_dup 2)] > >> UNSPEC_HTM_FENCE))] > >> "TARGET_HTM" > >> "tabort. %0" > >> - [(set_attr "type" "htm") > >> + [(set_attr "type" "htmsimple") > >> + (set_attr "power9_alu2" "yes") > >> (set_attr "length" "4")]) > > > > What determines if an insn is htm or htmsimple? > > > htm insns are cracked whereas htmsimple are not.
Sorry, I wasn't clear. That is what is the difference on p9, sure. But is there some pattern to this? Some difference that does not depend on a specific CPU implementation. > (rs6000_sched_init): Fix initialization of last_scheduled_insn. > Initialize divCnt/vec_load_pendulum. You missed divCnt here :-) > +(define_insn_reservation "power9-vecdiv" 32 > + (and (eq_attr "type" "vecdiv") > + (eq_attr "size" "!128") > + (eq_attr "cpu" "power9")) > + "DU_super_power9,VSU_super_power9") Does that work, the ! ? This looks much better :-) Okay for trunk; okay for 6 later. Thanks, Segher
